**BUG** I'm hoping you can help me with a problem I'm having running a netlist. It is for a UC384x series SMPS converter, converted from LTspice to ngspice. <http://sandbox.easyeda.com/editor#id=BHFfAy864> Running it, I get the "Simulation too large" warning *but I don't think that is the problem.* I have tried to run it in ngspice.com: <http://www.ngspice.com/index.php?public_circuit=4P00Ya> but that fails and gives me this error: "Can't use .control statements with ngspice.com." The problem there is that there are no .control statements in the copy that I have posted onto ngspice.com. I cannot spot anything that might be misinterpreted as a .control class of statement. This is why I think the problem may not be just because EasyEDA thinks the simulation is too large: I think there is something about the syntax that is wrong but I cannot see it and am not getting enough debug information to get any further. Here are the things I have done to try to debug the error: *I've put the whole netlist into different text editors to see if there are any hidden or mistranslated characters and found nothing. *I have tested the stuff in here: ~~~~ ******************************************************** * Quiescent current drain ******************************************************** Bqui1 vp 0 I=V(vcc_bad)*V(vp) / 30k + (1-V(vcc_bad))*V(vp) / 1.36k ******************************************************** * Supply for error amp gated with vcc_ok ******************************************************** *B2 0 ampvcc I=5 ; uncomment for amp frequency response test B2 0 ampvcc I=5*V(vcc_ok) ; comment out for amp frequency response test R3 ampvcc 0 1 C2 ampvcc 0 1p ******************************************************** * Uncomment the three lines below to carry out amp frequency response test *Btest1 0 half_ref I=V(ampvcc) / 2 *Rtest1 half_ref 0 1 *Ctest1 half_ref 0 1p ********************************************************* * SR latch, NOR gate (and Toggle flip flop for UCx844 / 5 devices only) ******************************************************** aadc1 [delcomp] [delcompd1] adc1 aadc2 [vcc_bad] [vcc_badd1] adc1 aadc3 [ref_bad] [ref_badd1] adc1 ** * SR latch (with all output states defined) * anorgate3 [osc_out PWM_Qp] PWM_Qn nor1 anorgate4 [delcompd1 PWM_Qn] PWM_Qp nor1 * apullup1 pullup pullup1 ; only used for UCx844 / 5 parts *atflop1 pullup osc_out null null null QNd1 tflop1 ; uncomment for UCx844 / 5 devices *anorgate1 [vcc_badd1 ref_badd1 osc_out PWM_Qn QNd1] updrvd1 nor1 ; uncomment for UCx844 / 5 devices anorgate1 [vcc_badd1 ref_badd1 osc_out PWM_Qn] updrvd1 nor1 ; comment out for UCx844 / 5 devices * adac1 [updrvd1] [updrv] dac1 ** * ADC bridge model * .model adc1 adc_bridge(in_low = 0.5 in_high = 0.5) ** * Pullup / down models * .model pullup1 d_pullup(load = 1p) ** * T Flip Flop model * .model tflop1 d_tff(clk_delay = 1n *+ set_delay = default 1n (unused) *+ reset_delay = default 1n (unused) + ic = 2 + t_load = 1p + clk_load = 1p + set_load = 1p + reset_load = 1p + rise_delay = 1n + fall_delay = 1n) ** * NOR gate model * .model nor1 d_nor(rise_delay = 1n + fall_delay = 1n + input_load = 1p) ** * DAC bridge model * .model dac1 dac_bridge(out_low = 0 out_high = 1 out_undef = 0.5 + input_load = 1p t_rise = 40n t_fall = 2n) ******************************************************** ~~~~ and each of the 8 subckts separately. They all work fine. (You can try the test jigs here: <http://sandbox.easyeda.com/editor#id=lA6QK2kCw|hnTb5mEyQ|drDYkG2M8|qwqjd7pHZ|qKgasK2Wd|VJDVd7pGY|HJj2o2eAW|Ox7tPN97s|RWw6GEXxv>) *I have also taken the whole netlist and removed or commented out each of the subckts in turn but the error persists. *I tried moving the .ends UC3843BEE statement so that the individual subckts were outside the main UC3843BEE subckt. Url: <http://sandbox.easyeda.com/editor#id=BHFfAy864> Browser: