Okay I have it tied down now.  Take any PCB and set **just one track** to have Design Rules spacing of 25mil, i.e. a high voltage line.  Then select the area and ask it to ground plane.  The planing algorithm seems to assume all the tracks are the same and places copper within 13mil (my usual low voltage spacing) of all the tracks, including the high voltage one.  DRC catches it but no idea how to fix it other than a very complicated ground plane outline