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Ground rats not connecting to ground pour
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honu.hank 8 years ago
I have a very simple 2 layer board where I've made the 2nd layer a ground layer using the copper pour. I can see that the component thru-holes are connected to the ground layer but the ground rats or air wires still show not routed and the Design Manager shows GND as not connected. I've seen others posting on tis but I don't see how to fix it. Here is the project https://easyeda.com/honu.hank/2_stage_preamp-OUu31ZXVv
Comments
example 8 years ago
Hi, This is private project or you have removed it, we can't follow. Can you post an image at here? BTW, make sure your ground pour is not an island.
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honu.hank 8 years ago
Thanks I didn't have sharing set right -try again
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example 8 years ago
You made a small mistake, but caused the big problem. You should use copper Area tool not solid region in the PCB tool. Please check https://easyeda.com/Doc/Tutorial/PCB.htm#CopperArea and https://easyeda.com/Doc/Tutorial/PCB.htm#SolidRegioninPCB out
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honu.hank 8 years ago
Thanks that was it - now ready to FAB
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dillon 8 years ago
OK. We have got your order, Will shipping after 3 days, and you will get a track number under your order. You can track them.
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ideaman4u 7 years ago
Seems that Rat Lines do not disappear if Solid Regions used even if named same as net region is replacing.
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eee11 7 years ago
@Ideaman4u any image to show that?
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andyfierman 7 years ago
Due to this bug: https://easyeda.com/forum/topic/Project_view_page_for_new_project_files_is_broken-BpVdvNHYg it is not possible to see your public project. If you send me a copy of your EasyEDA Source file as described in this post: https://easyeda.com/forum/topic/LM358N_simulation_shows_no_gain-moUcuoGYg then I can investigate the issue. Thanks.
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ideaman4u 7 years ago
First, EEE11, I just saw your post and apologize for not acknowledging it earlier. No, no image as I was still floundering around the the software when I thought I saw this phenomenon. Anyway, I would mention a few issues with copper pour that wasted a LOT of time on my part. Pours are wonderful for making PCBs simpler and more robust. I am referring to the classic (voltage pour on top and) ground pour on the bottom, principally. First, I misunderstood the Tutorial graphic regarding the copper pour feature. I THOUGHT it showed the pour EXCEEDING the the dimensions of the Board Outline (it doesn't). While the software will allow you to do this, it doesn't work. Your pour while appearing to be okay will not allow you to properly connect even if you specify the correct net. It shows no connection with most if not all components; it's flaky. Instead, you must make SURE the copper pour does NOT extend outside the Board Outline. Then it works fine. Second, DO NOT place tracks AND pours on the same net. The software does not like it and you will get both net issues and DRC issues. Note that once you have placed pours, you can turn off the Solid feature to allow easier inspection of component placement and tracks. This is fairly synonymous with having the pour as its own layer in other software. There is an apparent issue with GND being the default Net for a copper pour on either surface. Watch out for this if making other than a (bottom) GND copper pour. Hope this helps someone out there. For free, EasyEDA is truly awesome.
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andyfierman 7 years ago
This project: https://easyeda.com/andyfierman/Copper_Areas_demo-62b1305bafa64b76a06e446d0aa7ddce demonstrates that copper floods created using the `Copper Area` tool can: 1. be drawn outside the area defined by the Board Outline; 2. share edges (edges that drawn are on the same XY coordinates do not overlap); 3. must be assigned the same netname as the nets to which they are to be connected. The screenshot below shows that there are no DRC errors as a result of creating copper areas in this way: ![enter image description here][1] [1]: /editor/20170110/5874adfdeb17f.png
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ideaman4u 7 years ago
Weird. Until I very carefully made sure that the copper pour was inside the board outline, I could not reliably get rid of Ground and +V errors. If pour is outside of board outline, does this mean pour will actually extend to very edge of board? I ask because most fab houses don't extend pours to very edge of board; I think because can cause copper fill to separate from underlying board material. The net assignment is understood.
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andyfierman 7 years ago
Yes, I think there is a problem with copper areas not being inset from the board edges and also from each other: https://easyeda.com/forum/topic/Copper_areas_with_shared_edges_do_not_respect_clearances-Dd7CKSeAW I have not checked to see if this is fixed in the new V4.1.1 update.
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