In this way, maybe you can place a copper + soldermask on the one layer, then add a hole.

@dillon So it's not possible anymore to create one layer pads like in the picture below? I don't always work with copper planes...![example][1] [1]: /editor/20180214/5a83deda04914.png

Hello again guys. Please if you have some time, explain why did you turned a such a nice feature into a drawback? It is very frustrating to upgrade an old project by copying and paste one layer PADs, just because you can't create them anymore (not so professional). The second thing is that I have now two useless (not editable) parameters in the "Pad properties" bar (see attached picture) if I'm working only on one layer. Am I able to downgrade my EasyEDA version, so I can work like I used to? ![enter image description here][1] Thank you for your understanding and for you efforts, Alexandru [1]: /editor/20180216/5a86cb0da0243.png

Hi Alexandru, Some comments. * If you are working with only one layer then you can design the PCB on the Top or Bottom layer using pads defined as `All Layers` and just state on your PCB order that the PCB is to be single layer with copper on the Top or Bottom layer as required. For your double sided (or more layers) PCBs, it is not clear from your post if you are trying to create a copper area with a copper-free area inside it or if you are trying to create a copper area with a hole through the PCB inside it. * If you want to define an area of copper with a pad around it but no copper in the centre and no hole through the PCB then you can either use the `Arc` tools to define a circle of copper of some width and radius or simply place a `Solid Region` defined as `Cutout` in a single layer pad or a copper area to create an area with no copper. * If you want to define an area of copper with a pad around it on one layer but no copper in the centre and have a hole through the PCB then you can place a single layer pad and then place a `Hole` inside it. As long as there is no copper on the same net on the other side of the board (or any inner layers) which the hole passes through then the single layer pad will not be connected to any other copper however, I am not sure if it will still be through plated. You would need to contact Support directly to clarify that point. EasyEDA is designed to produce 2 or more layer PCBs. As such, a pad with a hole will automatically be through plated to join the pads on the top an bottom layers. A pad on a single layer will automatically be interpreted as a top or bottom layer Surface Mount pad: i.e. it will have no hole in it. From this point of view, a pad on a single layer with a hole in it must be interpreted as a through plated pad on all layers. A single layer pad with a copper-free area in it is different from a pad with a hole in it because the concept of a `hole` is a hole drilled hole through the PCB, not a copper-free area. * However, I agree that the way it is implemented at present should either be tidied up to remove the redundant parameters or simply revert to the way it was done in the earlier versions.

@andyfierman Thank you very much for your answer. I understand what you mean by this "hole concept" and it makes sense, but currently I have two major problems (or maybe frustrations)...one is technical specific and the other is more general: 1. I have some old projects in work, that were started in an earlier EasyEDA version (when I was able to create **one layer** PADs). Now I have to redefine some of the custom components and to update them with the **all layer** PADs...that means that on the other layer, some copper "rings" will appear and will reduce the space budget (it is easier to place traces between empty holes than between holes with unused copper rings). 2. If I'm not using EasyEDA for a long period of time and then I decide to continue working on some project, I have to relearn the menu and to get used with all the new changes...that is why I find very useful a downgrade possibility. Thank you very much for you effort, guys! I really appreciate what you are doing and I hope you understand my issue. Best regards, Alexandru

+1 Observing same issue. I've just discovered no single layer pads with holes. Many of my old component designs are now useless. I don't know if I can revise an old pcb without having to completely rework it. I think this change is a BIG step backwards IMHO.

@jtelect Hi, it seams that we have to do the double work for the old projects...:-/ It's frustrating because this very useful feature was available in the previous (early) versions... :-( I wish you good luck! Alexandru

Hi guys, Since my issue is still "on the table", for old and also for future projects, I'm asking you for new ideas that could help me. In order for you guys to get a better overview of my problem, I draw a fictive PCB example (not functional board).  As you can see there are some situations where the PADs of a footprint are not used on one of the layers (TOP in this case), but they become annoying obstacles for the design. In the example above, I'm not able to connect the TOP traces (from the right of the connector to left) without shorting the connector pins (assuming that narrowing the traces near the connector pin is not a viable solution here).    I see two possible future implementations for solving this issue: 1\. Restore the feature of creating one layer PADs\, like in the earlier versions\. 2\. Implement the possibility of setting the PAD's width separately for TOP and BOTTOM Basically I want to get rid of unused PAD's in order to gain more space on the PCB for routing the traces. I'm encountering this issue mostly with ICs, relays, connectors, mechanical switches, etc. (basically every thru hole component with high density pins). Please let me know if further clarifications are needed, because I'm really looking forward go on with my projects. Thank you very much in advance and keep up the good work, guys! :-) Alexandru

@Dutzu, "Basically I want to get rid of unused PAD's in order to gain more space on the PCB for routing the traces. I'm encountering this issue mostly with ICs, relays, connectors, mechanical switches, etc. (basically every thru hole component with high density pins)." If you are etching your own PCBs from PCB layout plots then you can create footprints using SMD pads and then place a hole in the centre of each pad using the Hole tool to act as a drilling guide. However, if you are having your PCB professionally manufactured then what you are proposing as a problem is a standard situation for all PCB tools. It is bad practice to design and then try to manufacture multi-layer (2 or more) PCBs with single sided pads and no through hole plating, The whole of the PCB industry is geared up to manufacturing boards with pads on all layers that are connected to each other through the hole in the PCB layer. There are some manufacturers who will make multi-layer boards with the pads removed from the inner layers but because it is more difficult to maintain a reliable through hole plating during board manufacture, this tends to make the boards much more expensive. There are a few ways in EasyEDA to deal with the issue of restricted routing space between pads. 1\. Reduce the track width in the the region through the pads\. You will have to create the track in at least 3 segments: two wide ones away from the width restriction\, one narrow one to pass through the width restriction; 2\. Create a version of the footprint with the minimum Multi\-layer pad outer diameter \(as recommended by the connector manufacturer\); 3\. If you must have a larger pad diameter on the opposite layer from the component mounting side then do the same as \(2\) and then place an SMD pad centred over the multi\-layer \(through hole\) pad\. Assign this pad the same pin number as the pad it it covering\. This will work OK if done within a PCB footprint but will generate DRC errors if you add the SMD pad directly in the PCB Editor and it may be removed when you do Update PCB from the schematic; 4\. Consider using rectangular or oval pads as you may be able to increase the spacing between the inner edges of the pads whilst still having sufficient pad width between the front and back ends of the pads; 5\. Design the layout to avoid this kind of restriction; 6\. Chose a wider pitch connector; 7\. Use an SMD connector and via to the other layer\(s\) Another possibility - but one which is not supported in EasyEDA - is to use an SMD connector and blind vias.

@andyfierman Thank you again for the fast response. I'm perfectly aware of all 7 statements that you presented and I totally agree with you, but I find very often the situation where the unused "copper rings" become annoying. It doesn't help me if the manufacturer can get rid of the unused pads in the process, since the constrain is on my side during the design. I think that I will go one with a method similar with something you proposed: " _If you are etching your own PCBs from PCB layout plots then you can create footprints using SMD pads and then place a hole in the centre of each pad using the Hole tool to act as a drilling guide."_ **Please let me know what can go wrong if I choose to place a VIA on a SMD pad, acting as a drilling guide.** Below are the possibilities:  Thank you very much for your time and input, Alexandru

@Dutzu If you place the via or multi-layer pad on the SMD pad, it will connect top and bottom layer, because of the via and multi-layer pad are plated, if you place the hole on the SMD pad, it only has a through hole on the smd pad, will not connect top and bottom layer.

@UserSupport Thank you very much. I don't have a problem if the hole is plated or not...I just need a smaller diameter (minimum possible) for the unused PADs. I wanted to know if I will encounter some issues by creating some custom footprints in this way. Best regards, Alexandru

@Dutzu That should cause the DRC error "Hole to Hole", but you can ignore it.

@UserSupport OK, I understand. I find it funny to have the error named "hole to hole" since there is only one hole (SMD pad has no hole) :))))...but I understand. Thanks again!

@Dutzu Sorry, it should be pad to pad, :) 

@UserSupport OK...In this case what should be done to place multiple thermal VIAs on a DPAK footprint without generating the error, for example? Thank you.

@Dutzu It happen on the PCB when you check the DRC error. That is becuase of two different objects have the different net. if they have the same net it won't show the DRC error.

@UserSupport Thank you very much and have a successful week! :-)

@Dutzu, "...what should be done to place multiple thermal VIAs on a DPAK footprint without generating the error...?" Please see: [https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1](https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1)

@andyfierman Thank you very much for the hint! FYI, regarding your previous statement: "_However, if you are having your PCB professionally manufactured then what you are proposing as a problem is a standard situation for all PCB tools._" I just checked and I saw that Altium Designer and Orcad Layout allows the multi-layer PADs and VIAs to be created with different diameters and shapes for top, inner and  bottom layer (I'm pretty sure that Eagle allows this also, but I didn't check yet). Nevertheless, I'm glad that I figured this out also for EasyEDA...it's a workaround that I think will fit my needs. :-) Thanks again, Alexandru

@Dutzu, If this feature is important to you, please post a Feature Request for it. :)