Make a symbol and footprint part. Something like this: 

@quickstar77, 1. Clone the original Teensy Footprint for editing; 2. Save it as TEENSY\_P1\_ONLY with a description explaining what it is for and how to use it \(see below\!\); 3. Mark the pad centres of one row of the P2 connector strip in the Document Layer; 4. Delete the P2 row of Multi-Layer pads from the footprint; 5. Save TEENSY\_P1\_ONLY; 6. Place the Schematic Symbol for a single row of the "Grove" connector, prefix P1, into your schematic; 7. Assign TEENSY\_P1\_ONLY to its Footprint attribute using the Footprint manager; 8. Set this symbol Convert to PCB = Yes; 9. Set this symbol Add into BOM = Yes; 10. Place the Schematic Symbol for the other single row of the "Grove" connector, prefix P2, into your schematic; 11. Set this symbol Convert to PCB = Yes; 12. Set this symbol Add into BOM = Yes; 13. Convert to PCB...; 14. Place the TEENSY\_P1\_ONLY footprint as required; 15. Align the Grove connector strip\, prefix P2\, over the Document layer pad centre alignment guides inside the TEENSY\_OUTLINE\_ONLY footprint; Done. This will: * add both "Grove" connector strips into the BOM; * pull both "Grove" connector strips into the PCB; * give you an outline on the PCB with the information you want. I haven't thought of a way to avoid them so if they do occur, ignore any DRC errors relating to footprints overlapping...

Thank you for the detailed instructions.  I managed to get it to work, I think.  I do have a whole list of DRC errors for all of the pins, traces, and headers on the 1 side, but the labels show up the way I want. But when I went to order it the preview looked fine so I'm hoping it won't matter.

Sorry, my step 15 should have said: "Align the Grove connector strip\, prefix P2\, over the Document layer pad centre alignment guides inside the TEENSY\_P1\_ONLY footprint;" However\, looking at your TEENSY\_P1\_ONLY PCB Footprint: [https://easyeda.com/components/TEENSY-P1-ONLY_82ccac176a954d3ca9c88bf2846d03d0](https://easyeda.com/components/TEENSY-P1-ONLY_82ccac176a954d3ca9c88bf2846d03d0)<br> <br> and the current state of your projects: [https://easyeda.com/quickstar77/teensy-grove-breakout-shield](https://easyeda.com/quickstar77/teensy-grove-breakout-shield)<br> <br> I am not surprised you have lots of DRC errors because you have not followed the procedure I described. You have also made life unnecessarily complicated by editing the pins names and numbers on your connectors in the schematic and using names rather than simple sequential numbering in the footprint\. Matters are also confused by your switching the prefixes of P1 and P2 to TOP HEADER and BOTTOM HEADER which loses any sense of the why the TEENSY\_P1\_ONLY footprint is so named\. Here is a DRC error-free copy of your project done after reverting the connector names and then all the P1 and P2 connector pins and pads back to simple numbering: [https://oshwlab.com/andyfierman/teensy-grove-breakout-shield](https://oshwlab.com/andyfierman/teensy-grove-breakout-shield)

Wow that's amazing that you did that for me.  I renamed things because because the source teensy I was using had the pins renamed but thank you.