How to avoid DRC errors when connecting to PCB Footprints (a.k.a. PCB Libs)
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andyfierman 7 months ago
The basic problem when constructing PCB Footprints (a.k.a. PCB Libs) is that anything made of copper in a PCB Footprint that is not a pad will generate a DRC error with surrounding or connecting copper on the PCB. Here are some rules for making a PCB Footprint that will avoid generating these DRC errors: 1. Everything made of copper - including any connections between pads and mounting holes with copper around and/or through plated - must be made using Top, Bottom or Multi Layer pads, whether round, oval, rectangular or polygons and editing the points; 2. Holes without copper should be made using the Hole tool or Solid region set as Board Cutout; 3. All pads should be numbered but different pads can have the same number. For example, for a TO-220 packaged power transistor which has 3 pins on the symbol (CBE or DGS) but has 4 electrical connections to the pins and the tab that need to be mapped onto 4 pads so two of the pads can have the same number assigned to them; 4. All pads that are connected together by copper (see (1) above) must have the same number; 5. Do not try to use vias in a PCB footprint. Use a multilayer pad set to the same dimensions as a via (for more on this, see: [https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1](https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1)); 6. Because they cannot be assigned pad numbers, PCB Footprints should not be constructed including the following copper elements of Tracks, Arcs, Copper Areas, Solid Regions, Rectangles, Circles, other predefined shapes, Text or imported images. If a PCB Footprint containing such elements is then placed on a PCB, wherever a track or copper area crosses or passes too close any of these elements, it will generate DRC errors. The only exception to this is when such elements are placed within and completely surrounded by a pad so that they cannot be connected to. An example of this is shown in: [https://easyeda.com/andyfierman/avoiding-drc-errors-in-footprints](https://easyeda.com/andyfierman/avoiding-drc-errors-in-footprints);  7. Do not assign Nets to any part of a PCB Footprint: they will generate DRC errors because there is no guarantee that a net with the same name as that assigned to a pad in the Footprint, will be connected to that pad by everyone who uses that Footprint. For example, what one user may call GND in a PCB Footprint, may be connected by another user, to a net in the PCB called GRND, Earth, 0V or something entirely different like VSS; 8. As described in (3) above, the Schematic Symbol for a device may have fewer pins than the number of electrical connections to the physical package. For example, discrete MOSFETs usually have only a gate, source and drain connection but many are packaged so that although there is a Gate is connected to a single pad, the Source may be connected to 3 pads, which are all directly shorted together on or within the package and the Drain to 4 pads. To avoid over complicating the Schematic Symbol - and therefore cluttering up the Schematic - this is easily and most effectively handled by mapping each pin on the Schematic Symbol onto one or more pads, assigned the same number, on the PCB Footprint; 9. A PCB Footprint must not have fewer pads than the number of pins on the device that is to be placed on it. Do not omit pads for unconnected or NC pins on the device: they are often required for mechanical or thermal stability. This must include things like, for example, ground and shield pins on USB and Ethernet connectors. Below is a topic that illustrates some of these issues and their solutions according to these rules: [https://easyeda.com/forum/topic/Drc-errors-with-library-component-f42b0deca29a47df944623bbeff22184](https://easyeda.com/forum/topic/Drc-errors-with-library-component-f42b0deca29a47df944623bbeff22184) Also, search for BSC042N03LS and then analyse and compare the three symbols and footprints: As a 3 pin symbol mapped onto an 8 pad footprint: ![image.png](//image.easyeda.com/pullimage/EDFtqOPOMi40w1cONfPknw9ll4HV1NNYes4f0asM.png) As an 8 pin symbol that has to be mapped onto an 8 pad footprint: ![image.png](//image.easyeda.com/pullimage/dEdWlYWuqizrLdPG0Zl9zfxqOVKfYgYIPBEc7uWF.png) As an 8 pin symbol mapped onto an 8 pad footprint: ![image.png](//image.easyeda.com/pullimage/CAnHLiVTIMzglpsrDhlgu5OznP22dRY5iKQyqZMh.png)
Comments
Henrik Larsen 2 months ago
Term 6 above is unclear to me. Please elaborate....
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Henrik Larsen 2 months ago
I tried to follow Term 5 above to avoid DRC errors, but get "Via Diameter" DRC error on my multilayer pads. I'm using a small diameter for the thermal multipayer pads on the footprint, and are using larger via requirements in my PCB design rules. ~~~~
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Henrik Larsen 2 months ago
@maximumiq BTW: I am also getting via drill diameter DRC errors on the same thermal multilayer pads.
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andyfierman 2 months ago
@maximumiq, This HowTo explicitly says do not try to place vias in pads. Use small pads instead.
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andyfierman 2 months ago
@maximumiq, If you are getting "Via Diameter" DRC error on multilayer pads, where are these vias and how are they being used? Are they in a pad that you have placed directly on the PCB or have you added them inside a pad that is part of a PCB Footprint? You need to provide more information about your particular situation.
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andyfierman 2 months ago
Another way to state term 6: The only way you can place Tracks, Arcs, Copper Areas, Solid Regions, Rectangles, Circles, other predefined shapes, Text or imported images (as copper, not silkscreen) in a PCB Footprint and not generate DRC errors, is to make a top or bottom layer pad and then create a copper free area inside it using a Solid region set to "No Solid", and then place your elements inside that copper free area. The "No Solid" region must be completely enclosed by the pad that it is placed in and the elements must all be inside - and not touching the edges of - the "No Solid," region. At some point I will try to clarify term 6 and add a picture.
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Henrik Larsen 2 months ago
@andyfierman After some experimenting, I was successfull in creating a specific LGA footprint, with cooling VIAs (pads with holes), with individual pads having correct pastemask and soldermask. But it was difficult I think. Out of the head, this is what I did: 1. Defined each pad for the footprint connections as square pads, grouped them by setting respective netnames 2. Added solidregions to enclose the pads in groups. Each solid region I converted to a pad and set the same netname as the pads inside 3. On each polygon pad I set both masks offset to -xxx mil to completely remove the masks from the large pad, revealing the masks on the smaller pads inside 4. Added a number of circular multilayer plated pads and set the netname to the same as the groups netname for each of these as well 5. Changed circular multilayer pads size to not break PCB DRC rules See below for clarity. This footprint is for the LTM8040. ![image.png](//image.easyeda.com/pullimage/4quReu7JcJoEfzc2RFWl3zDuxLWaU8AgKYyihtjA.png)
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Henrik Larsen 2 months ago
@andyfierman I don't understand how you would connect traces to the component if the base of the footprint must be a top and bottom pad completely enclosing everything inside.
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andyfierman 2 months ago
I think you still misunderstand what I  am referring to when I  talk about a pad completely  enclosing an element.  That is for a special case. Reading your description it sounds like you have made things more complicated than you needed to but I am not sure because  I  do not have access to a pc until Monday @maximumiq to try to work out what exactly you are doing. To add thermal or electrical "vias" as pads into the mains pads of a PCB Footprint is very straightforward and is described in the rest of my howto about adding thermal and electrical vias to pads: [https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1](https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1)
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andyfierman 2 months ago
@maximumiq, Can you share a public project to demonstrate what you are trying to achieve?
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andyfierman 2 months ago
@maximumiq, Updated my description for section 6 above.
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