@timicek, Can you provide either a translation of, or a link to, the diagram you have posted? It will help to understand the exact reasoning behind the layout illustrated. Do you need to apply this to a particular chip and therefore do you have a link to the device datasheet that describes this technique? BTW: By coincidence, I am in the process of writing a Howto about a way to avoid tracks becoming embedded into a surrounding copper area assigned to that net. It is written to illustrate the creation of Kelvin Voltage Sensing tracks for 4 wire sensing but is equally applicable to your situation. I will post back when it is ready.

Essentially the answer is your option (2) which works fine because you are not forced to merge the two segments into the same netname.. Please see: [https://easyeda.com/andyfierman/4-wire-sensing-using-the-kelvin-connection](https://easyeda.com/andyfierman/4-wire-sensing-using-the-kelvin-connection)

@andyfierman no\, \(2\) does not work \- here EasyEDA translates GND\_CMOS to GND and again\, the GND\_CMOS is  addtionally supplied by several connections to the GND ground (copper) plate (in case it is drawn in the PCB) and the inner loop (which should shield bad frequencies of the working chip) is disturbed! This is not a special technique. You should supply each decoupling capacity - which is each capacity of any CMOS chip - by such an closed inner loop. For example have a look at my mentioned article (here in a translated version): [https://translate.google.com/translate?sl=de&tl=en&js=y&prev=_t&hl=de&ie=UTF-8&u=http://www.lothar-miller.de/s9y/categories/14-Entkopplung)&edit-text=](https://translate.google.com/translate?sl=de&tl=en&js=y&prev=_t&hl=de&ie=UTF-8&u=http%3A%2F%2Fwww.lothar-miller.de%2Fs9y%2Fcategories%2F14-Entkopplung%29&edit-text=)

@andyfierman I have read your mentionwed article: [https://easyeda.com/andyfierman/4-wire-sensing-using-the-kelvin-connection](https://easyeda.com/andyfierman/4-wire-sensing-using-the-kelvin-connection) nice :-) There you mentioned (3) is the right solution and I have live with the raised DRC errors :-(

@timicek, I may have misunderstood exactly the steps you carry out in your options (2) and (3) but the scheme I described in my Howto does not skip any nets in the schematic. They are all placed as usual, the only unusual step is to rename just the segments of the tracks in the PCB that need to be kept isolated from - and before building - the copper areas and then (optionally) to rename them back to their parent net names immediately before the _final_ Update PCB... and DRC as described in (6) in: [https://easyeda\.com/andyfierman/Welcome\_to\_EasyEDA\-31e1288f882e49e582699b8eb7fe9b1f](https://easyeda.com/andyfierman/Welcome_to_EasyEDA-31e1288f882e49e582699b8eb7fe9b1f) (direct link: [https://easyeda\.com/andyfierman/Essential\_checks\_before\_placing\_a\_PCB\_order\-de51f1401cec4bd2896ea835aca67db8](https://easyeda.com/andyfierman/Essential_checks_before_placing_a_PCB_order-de51f1401cec4bd2896ea835aca67db8)) and taking care to **not** rebuild the copper areas once the nets have been reset to their parent net names. That way the _final_ DRC will not show any errors for the copper cleared nets. :)

Just to clarify: "...the only unusual step is to rename just the segments of the tracks **and pads** in the PCB that need to be kept isolated from - and before building - the copper areas..."

@andyfierman thanks for your advice :-) I think your mentioned method to rename and then re-rename all isolated GND loops is for me too error-prone since my PCB includes several ICs (easy to forget something), so I live with the DRC. Is there a problem to manufacture a non-valid PCB by your in-house manufactor JLC PCB?

As long as your Gerbers are OK (best check using gerbv: [https://docs.easyeda.com/en/Export/Export-Gerber-Files/index.html#Gerber-View](https://docs.easyeda.com/en/Export/Export-Gerber-Files/index.html#Gerber-View)) then JLCPCB should have no problem.

Hmmm. I am not entirely convinced by the article that you linked to. I think it is missing part of the argument about impedances and return paths and, as a result creates a problem that does not need to be solved. If you look further down the page in the article, there is an image that shows an alternative that would almost remove the problem: [http://www.lothar-miller.de/s9y/uploads/Bilder/Entkopplung_OK2.jpg](http://www.lothar-miller.de/s9y/uploads/Bilder/Entkopplung_OK2.jpg) Here's a simple circuit that can be used to demonstrate this form of decoupling on a PCB:  Which can be achieved in a 2 layer PCB with a bottom layer VDD flood and a top layer GND flood by renaming the GND trace to - and the GND pad on - pin 4 of U1 to VSS like this:  but that of course causes a couple of DRC errors. However, this decoupling routing scheme does not minimise the inductance in the ground return path of the device to the decoupling capacitor. There is a higher inductance in that path than there needs to be and so there will be more ground bounce. A simple change can simplify the whole layout and DRC task and improve the grounding all in one go. If you add one more ground connection, which will actually reduce the inductance and therefore the impedance of the return path from the ground pin on the device to the ground side of the decoupling capacitor then the wole issue of having to keep the capacitor ground routing clear of the ground copper flood goes away. No special net renaming. No DRC errors. At the same time it will reduce the impedance from the VSS pin 4 on U1 back to the ground end of decoupling cap C1 and so reduce ground bounce that the original scheme introduces by inserting an inductance (due to the IC pin to cap to ground traces) in series with every ground pin of the IC:  I'll post the link to the project this is from when I've finished the sims showing the effects of ground bounce etc.

Obviously it depends on the actual IC and application and Timicek never gives a part number, but some designs do need the ground lead inductance you are trying to reduce to form a low pass filter with the bypass capacitor.  MOSFET drivers spring to mind, but also some r.f. designs where you would take the ground all the way through the bypass capacitor and then to the circuit being driven.  Flooding everywhere with a single ground plane isn't always the correct solution, and indeed in switchmode PSUs is almost the worst possible solution.

"Flooding everywhere with a single ground plane isn't always the correct solution, and indeed in switchmode PSUs is almost the worst possible solution." Why?

Because in a switchmode PSU or motor driver using a half (or full) bridge, to avoid ground bounce turning the lower output transistor back on, the 0V of the MOSFET driver IC should be taken directly to the lower MOSFET source connection and nowhere else - effectively that is a local star point.   There's also a similar arrangement for the top MOSFET but of course as that's the output nobody thinks of ground plaining that and it's usually done well. The reservoir electrolytic -ve should also approach this point in the same way, but it is the output MOSFET source that is the critical reference point.  Flooding a single ground place creates all sorts of unexpected potential differences.  My boards often have five or more grounds all making their way back to this one point. There's an excellent application note on this from Infineon - see page 12 & 13 on [https://www.infineon.com/dgdl/irs2003pbf.pdf?fileId=5546d462533600a401535675afec2780&usg=AOvVaw3C820-DsnhEao1TGtHu9-v](https://www.google.co.uk/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=2ahUKEwiDwZjDkfPeAhXvYt8KHQ8ODUgQFjABegQITRAC&url=https%3A%2F%2Fwww.infineon.com%2Fdgdl%2Firs2003pbf.pdf%3FfileId%3D5546d462533600a401535675afec2780&usg=AOvVaw3C820-DsnhEao1TGtHu9-v) They even suggest running the drive and ground reference as a twisted pair, though that seems a little excessive to me - I just run them in parallel and ensure they are the same length. Of course you still need a ground plane over the whole board, but in fact very few components connect to it, it's purely a screen with no significant currents running through it.

Oh one other point, in CMOS half of the transistors are referenced to the positive line, not the ground.  So a good Vcc plane is just as important as the ground.  The example you show has a very skinny Vcc and ground everywhere.  Not a good balance, but it may not be a CMOS IC of course.

@MikeDB, Is the Infineon Apps note you're referring to this one (originally International Rectifier)? Application Note AN-978: HV Floating MOS-Gate Driver ICs: [https://www\.infineon\.com/dgdl/Infineon\-HV\_Floating\_MOS\_Gate\_Drivers\_AN978\-AN\-v01\_00\-EN\.pdf?fileId=5546d462533600a40153559f7cf21200](https://www.infineon.com/dgdl/Infineon-HV_Floating_MOS_Gate_Drivers_AN978-AN-v01_00-EN.pdf?fileId=5546d462533600a40153559f7cf21200)

@andyfierman Yes that's it.  Seems to be in several different locations but same text.  I think Infineon are still choking on absorbing IR.  They've sold off the Singapore and Newport Wafer fabs and transferred production to their own fabs but the documentation is still a bit hit and miss.

Why not just use a keepout area on the ground plane? This will force you to need to draw the traces manually, the plane will not be able to reach the capacitor. Here's an example I made: [https://easyeda.com/cjohnson/DecouplingCapacitor](https://easyeda.com/cjohnson/DecouplingCapacitor)

It produces no DRC errors, and is very easy to do. 

@cjohnson, There may be occasions where the net renaming is easier simply because the shape needed for the cutout is difficult to create but many thanks for sharing a nice alternative scheme.

@everybody Perhaps I'm missing something but on other tools I no longer have access to, I've always found it best to lay out the IC positions by hand and place the decouplers and their tracks at the same time.  I always had them set up as macros.  Only then do you let the auto-router rip. (which on EasyEDA seems almost pointless :-( Or is it a different DRC problem I just haven't seen yet ?

Also what are these ICs you have that have VCC and GND so conveniently located on the same side of the package ?  In the old days they were on opposing corners and nowadays they always seem to be in the centre on opposite sides.

@MikeDB, The thing to never lose sight of in any decoupling in high speed signal and fast edged switching applications - such as datacomms, laser driving, SMPS and Class D amplifier applications - is that the objective is to minimise the impedance of the supply paths presented to the supply pins of the device. Understand and get that right and everything else in terms of EMC, Signal Integrity and Power Integrity will be optimised. EMC, Signal Integrity and Power Integrity are after all the same effects just at increasing ordes of signal magnitude. For supply decoupling, the most important paths are between the supply pins on the device and the end caps of the associated decoupling capacitance because this is the closest reservoir of charge to the device. Further decoupling can be made up from larger and possibly higher ESR and ESL capacitance placed further away. At least for the local supply decoupling, on the scales of routing to many devices on a PCB, the resistance of the traces - even allowing for the increased skin effect resistance due to the high frequency content of the switching edges - will be negligible so the impedance is dominated by the inductance of the tracks. The obvious way to minimise the inductance of these supply paths is to keep them direct, short and wide (compared to the width, i.e.  a high aspect ratio). Transferring from one layer to another introduces vias that present additional inductance in the path so any layer transfers that are unavoidable must be made using multiple vias to effectively place their additional inductances in parallel. Currents due to the high frequency content of fast switching edges will take the lowest impedance path to get to the destination and to return to the signal and ultimately the power source. The lowest impedance path can be in a wire or trace immediately adjacent to or, in the case of ground or power planes, below the signal trace. Note however, that this does not mean that these currents will take the physically shortest route. For example, the high frequency return path for a trace driven at one end by a signal source at one end an terminated in some form of load at the other and routed in a "U" shaped path across ground plane will be under the trace and not straight across between the ends of the "U". In other words, the return current will follow exactly the same path as the signal current in the trace. Since the supply pins are effectively in pairs because for each supply pin there is usually an associated ground pin, there is also the equally important consideration of minimising the inductance created by the area enclosed by the loop formed by the supply traces between the pins on the device and the nearest decoupling capacitor. Anything that increases the loop area whether obviously in routing of the traces or less obviously in the continuity of the ground plane, for example by forcing the return current to have to flow round the edges of a hole or a slot in the ground plane, increases loop area and hence the inductance. Conversely, anything that increases the aspect ratio of the traces or reduces the loop area enclosed by them such as by placing the traces close together in the same plane or by routing them over a ground plane reduces the inductance. Once these basic principles are understood it can then be seen how they can be extended to minimise the impedance of any path where there are fast switching edges irrespective of whether they are traditionally considered as signal or power. Examples of such paths include but are not limited to: 1. between the input capacitance and the switching device in an SMPS and the associated ground return path; 2. between the switching and rectifier devices and the output capacitance in an SMPS and the associated ground return path; 3. from the gate drive output to the gate of a switching device and the return path from the source or emitter back to the gate driver; 4. the routing of even low frequency signals but with fast edge speeds across and between layers on PCBs with complex plane areas. The example I created was to answer timicek's particular question rather than try to post a more generic guide to high speed decoupling and PCB layout. The "inverter" device does not represent an actual device. It is a simulation model packaged such that it matched the PCB examples in the OP's quoted link: [http://www.lothar-miller.de/s9y/categories/14-Entkopplung](http://www.lothar-miller.de/s9y/categories/14-Entkopplung) It was created with a view to demonstrating some aspects about high speed layout. Simulations and representative PCB layouts for this have yet to be developed. I think the the photo in the linked article is of an ST ST10F276Z5 device which has a number of supply pin pairs at various points along each side of the QFP package: [https://www.st.com/content/st_com/en/products/microcontrollers/legacy-mcus/st10-16-bit-mcus/st10f276z5.html](https://www.st.com/content/st_com/en/products/microcontrollers/legacy-mcus/st10-16-bit-mcus/st10f276z5.html) [https://www.st.com/resource/en/datasheet/st10f276z5.pdf](https://www.st.com/resource/en/datasheet/st10f276z5.pdf) with some layout guidelines here: [https://www.st.com/content/ccc/resource/technical/document/application_note/7f/d2/06/96/22/42/47/ef/CD00165880.pdf/files/CD00165880.pdf/jcr:content/translations/en.CD00165880.pdf](https://www.st.com/content/ccc/resource/technical/document/application_note/7f/d2/06/96/22/42/47/ef/CD00165880.pdf/files/CD00165880.pdf/jcr:content/translations/en.CD00165880.pdf) There isn't an autorouter I trust to not mess up some critical aspect of design for EMC, Signal Integrity or Power Integrity so I don't use them. Besides which, by the time all the components have been placed, the decoupling placed, the critical nets routed, the ground and power planes shaped and placed, the layer signal and return path transfer vias placed, there's not a lot left for an autorouter to mess up anyway. :)

I should clarify an equally important and very closely related aspect of the discussion above which is that the same behaviour of signal and return paths following the path of least impedance is the fundamental to understanding signal propagation along transmission lines. Understanding transmission lines underpins the design of impedance matching (as opposed to impedance minimisation) for high speed and RF signal paths and crosstalk minimisation which are also essential parts of successful design for EMC, Signal and Power Integrity.

I think I agree with 99% of what you say, but stop at "or by routing them over a ground plane reduces the inductance." No **local** current should ever go over the ground plane - it is purely a means of shielding and of connecting local ground stars together.  As soon as you have random signals on the ground plane you've lost the battle no matter what the frequency, but especially in r.f. as they will propagate everywhere you don't expect them to.   But you sort of allude to this with your mention of matching transmission lines - obviously this is near impossible if you use the ground plane as one of the lines. I'll also add that in high end audio there are two schools of thought but one says no audio signal ever even sees the ground plane - it's purely there to shield against crosstalk and source power.  I'm in that camp.

"No **local** current should ever go over the ground plane - it is purely a means of shielding and of connecting local ground stars together.  As soon as you have random signals on the ground plane you've lost the battle no matter what the frequency, but especially in r.f. as they will propagate everywhere you don't expect them to....your mention of matching transmission lines - obviously this is near impossible if you use the ground plane as one of the lines." Sorry Mike but nearly 45 years experience of high speed signal and power design, backed up by Howard Johnson's High Speed Digital Design and High Speed Signal Propagation books and courses,  Doug Smith's course in High Frequency Measurements in Signal integrity, Design and Troubleshooting, Bruce Archambeault's course on Fullwave Modeling for EMC and Signal Integrity and Rick Hartley's course on Signal Integrity and EMI Control in High-Speed Digital Circuits begs to differ on the first of those points and flatly contradicts the second. :)

@andyfierman Oh well I have about 45 years as well working with some of the top companies in the industry so we'll just have to differ.

@MikeDB, I can live with that. Your tolerances on matching transmission lines may be a little tighter than most of the digital signal applications can live with and you may also be dealing with signals at much lower levels so again the crosstalk limits may be tighter too.

A very important point about things like decoupling and other layout requirements both at the Schematic and the PCB layout is to read, understand and implement the manufacturer's recommendations for each device or collection of devices. This will usually be given in the device datasheets but more detailed information may be given in additional applications notes and design guides. This point is also made in the Essential Checks sections (4), (5) and (6) in: [https://easyeda\.com/andyfierman/Welcome\_to\_EasyEDA\-31e1288f882e49e582699b8eb7fe9b1f](https://easyeda.com/andyfierman/Welcome_to_EasyEDA-31e1288f882e49e582699b8eb7fe9b1f)

@andyfierman Thanks for your nice explanation and short tutorial :-)

@timicek, And for MikeDB's very useful contribution too.

@MikeDB The IC I used in my quick and dirty example was an RS485 driver. Most of the stuff I use is in the 100+ pin packages for uC's. Always have multiple VCC/VSS pins.