I did what you recommended for TOSHIBA 2-5Q1A package for a MOSFET with 8 pins.  but, I cannot get rid of ratlines even though the pads (4 small ones on a big centered one) are connected to drain pins and have the same net name and pin number. Any advice?

Here is the package, 

Hello - Thank you Andy, this is how I built my shape. Peter

If it's for thermal reasons, you probably also need to change the solder mask on the bottom of the board as thermal vias aren't much use if covered in solder resist.  For total reliability, you should duplicate any heat soak area on top, bottom and any inner planes so that there are no thermal stresses across the PCB thickness.  PCBs are much better nowadays but in the old days they often started delaminating if you heated one side only.

To explain a bit more about Mike's suggestion that "you probably also need to change the solder mask on the bottom of the board as thermal vias aren't much use if covered in solder resist.": If a thermal via is clear of solder resist (a.k.a. solder mask) on both top and bottom layers of the PCB then solder can flow into and fill the via hole. That then adds a useful low thermal resistance path from the layer that the thermal pad of the device is soldered to through to all other layers. If the via is covered with solder resist on one or both sides of the PCB then solder cannot flow into the via holes to fill them so the thermal resistance is much higher because it is only through the thin copper plating inside the hole. Covering a via on one side only is also not a good idea because any solder that does try to flow in from the uncovered side can cause the gas trapped in the hole to rapidly expand and blow the solder resist off the covered side. This can leave small areas of bare (unplated) copper exposed to corrosion and may also stress solder joints of any device that is placed on the other side of the board over the hole that has "blown". One aspect of the design of both thermal and electrical vias that does not seem well documented is that for best thermal and electrical conductivity, the vias should be solidly connected into their surrounding copper areas but this then means that more heat has to be applied to make a good solder joint to the device's pad. Adding thermal relief or heat shunts (spokes) to the vias makes it easier to solder the device but of course significantly increases their thermal and, depending on quite what currents may be flowing through the pad, the electrical impedance of the connection to the copper area. Many devices advise the use of multiple vias connected to multiple copper planes and some advise on the size and number of vias and the plane areas but I don't recall seeing anything that advises on heat shunt dimensions as a compromise between electrical resistance for signal and power integrity purposes versus thermal resistance for manufacturability.

Yes I should have said remove solder resist on both sides but in the example shown I assumed it was removed already for the transistor tab.

Andy's comment got me playing and as far as I can see if you use Create solder mask for a via it does so on top and bottom anyway, and I can't see a way to delete it from one side anyway.

A big problem with this approach is this: If I set the inner planes pad connection type to Spoke so that general parts are easily soldered, then this plane will form spokes to all Pads but solid connections with Vias. I think this behavior is good in the first place. But when using pads instead of vias in the footprint for thermal Vias, it will make spoked internal connection which is a little dumb. So then you would need to place additional areas either in the footprint or the PCB to make solid contact to the thermal vias.. What EasyEDA really needs is a a property for all Through Holes (Multilayer Layer) that allows to override the plane connection behavior of the planes.

@tobalt, "So then you would need to place additional areas either in the footprint or the PCB to make solid contact to the thermal vias.." If the thermal pads are required to have a solid connection to surrounding copper on other layers then the way to deal with this is to set the main pad (within which you place the multi-layer thermal pads) to be a multi-layer pad. Then if you have spoked connections to the surrounding copper, the pad within which the thermal pads are placed will be connected by spokes but will ovelap any spokes formed around the thermal pads. One point to be careful of is that if the thermal pads are placed too close to the edge of the main pad then the cutouts between the normally hidden spokes for each each thermal pad will be visible around the edge of the main pad making it look like the perforations around a postage stamp. An alternative to all this would be if the vias could be assigned pad numbers. So I have created a Feature Request for this: [https://easyeda.com/forum/topic/Add-Pad-Number-attribute-to-Vias-66fa7b37b26049a0b187d531a7692184](https://easyeda.com/forum/topic/Add-Pad-Number-attribute-to-Vias-66fa7b37b26049a0b187d531a7692184)

@andyfierman. Yes, the footprint pad (e.g. on the top layer would solidly contact to the multilayer through hole pads. BUT\, the multilayer through\-hole pads would not solidly contact to e\.g\. Inner layer GND planes once you place the footprint on the PCB\. This is pointless\.\.\. Why have \*thermal\* vias if they contact to the planes with thermal traps\.\.\. To achieve this solid contact on all those planes where you want it, you need to place solid areas on all layers where you want solid contact. It is also not possible to tell an area to apply to more then one layer. and YES, via net names in footprints would solve this issue. Ill second your request.

"To achieve this solid contact on all those planes where you want it, you need to place solid areas on all layers where you want solid contact. It is also not possible to tell an area to apply to more then one layer." That is exactly why I suggested using a multi-layer pad for the main pad within which you place the additional thermal pads instead of a top or bottom layer only pad: the main pad then exists on all layers and not on just the top nor bottom layer.

@tobalt @andyfierman If the footprint is system library, please tell me the name, I will fix it, the footprint should not have vias, that should use pads for instead. if the footprint is your own, please use pads, not vias, at next release, we will remove via entry for PCBlib.