Hi. I am new to EasyEDA. I am now trying to make an adder according to this report: [https://www\.researchgate\.net/publication/256373597\_A\_high\_speed\_8\_transistor\_Full\_Adder\_design\_using\_novel\_3\_transistor\_XOR\_gates](https://www.researchgate.net/publication/256373597_A_high_speed_8_transistor_Full_Adder_design_using_novel_3_transistor_XOR_gates) However, in this adder, the W/L ratio of the MOSFETs is a key factor. Therefore,  I need to specify the width and length of the transistors. Otherwise, the simulations show that the voltage will anyway be zero at output regardless of the input. How can I do so? Thanks! P.S. Here is the link to the project: [https://easyeda.com/Wetitpig/Adder](https://easyeda.com/Wetitpig/Adder), and also how to do simulation with the circuit? 大家好！我刚刚开始用EasyEDA。我现在打算根据这份研究报告画一个加法器：[https://www\.researchgate\.net/publication/256373597\_A\_high\_speed\_8\_transistor\_Full\_Adder\_design\_using\_novel\_3\_transistor\_XOR\_gates](https://www.researchgate.net/publication/256373597_A_high_speed_8_transistor_Full_Adder_design_using_novel_3_transistor_XOR_gates) 可是，我必须更改MOSFET晶体的长度和宽度，才能令这个加法器正常运作。请问我可以怎样更改晶体长和宽呢？ 除此以外，我可以怎么样可以模拟一次加数呢？谢谢！ 以下是我的加法器的线路图：[https://easyeda.com/Wetitpig/Adder](https://easyeda.com/Wetitpig/Adder)