The first part of your question is answered here: https://easyeda.com/Doc/Tutorial/PCB.htm#Copper-Area `is possible to specify a filled and capped (filled with resin and then capped with copper) thermal via as well?` It is not possible to define this within the PCB design file itself and I don't think the manufacturing processes that EasyEDA uses can support that type of via-in-pad construction (like that shown here: https://www.pcbuniverse.com/pcbu-tech-tips.php?a=5). `I'm wanting to create thermal vias under an IC` I assume you mean vias in a pad that are used as a heatsink for the extended pads found in some IC packages? In other words, you do *not* want these vias to have thermal shunts to the pads they are within? You can do this easily in EasyEDA but the resulting vias in the pad are not displayed very well. You simply place the pads where you want within the area that will be occupied by the pad and then place the (usually) rectangular pad over them. Have read of: https://easyeda.com/forum/topic/Link_SMD_pad_to_bottom_layer-c0UcuLrXf then a careful look at: 10MMPAD in the library. and also take careful note of how the pads and the vias are named. Don't put the vias too close to the edges of the pad or they will break up the copper area or tracks that try to join to the pad. Play about with a cloned copy to see what happens.

Sorry, mean to say `and also take careful note of how the pads and the vias are left unnamed.`