Hi vkbs,

Welcome to EasyEDA.

Sorry but you have not made your project public so only you can see it.

I suspect the problem will be that you have not found and used Spice Symbols i.e. schematic symbols which have spice models associated with them.

How to share your project and to find simulatable components and to run a simulation is all explained in the links given in:

https://easyeda.com/andyfierman/Welcome_to_EasyEDA-31e1288f882e49e582699b8eb7fe9b1f

There are examples in the simulation and some more here:

https://easyeda.com/andyfierman/How_to_use_EasyEDA_Schmitt_Trigger_input_logic_gates_as_an_oscillator-lSQqYPXR9

https://easyeda.com/example/Easy_logic_device_simulation_in_V2_3_x_onwards-RaKIG2oJ5

Hi Andy
Sry, I already got further, managed to do a simulation: https://easyeda.com/editor#id=804fa16111214766a944fdbf9afee334

But the output is always the same, no matter what values I use for C1, R1. Cycle is always ~76ns
Any idea?

Hi vkbs,

Run the sim for longer: Stop time = 4000ns.

I have to say this is an unusual way to make an oscillator using Schmitt trigger input gates.

The usual configuration is as shown in:

https://easyeda.com/andyfierman/How_to_use_EasyEDA_Schmitt_Trigger_input_logic_gates_as_an_oscillator-lSQqYPXR9

In your circuit, if you look at the junction of the 40pF and 10k then you will see that the voltage swings above the 3V rail and below ground. This is bad practice, certainly unless there is a current limiting resistor in series with the first gate input because at least, the swing is clamped by the input clamp diodes to supply and to ground and at worst, it may force the device into latchup and so destroy the device by shorting out the supply to ground through it.

• It may help to have a read of:

https://www.fairchildsemi.com/application-notes/an/an-118.pdf

Hi Andy
Many thanks for your prompt answer and your hints! I changed my oscillator and it seems better now. I want to avoid having the cap on GND to avoid interferences by antenna phenomenon.
(I'm trying to build a capacitive moisture sensor)

Ah, ok. So that 40pF cap isn't a physical part but is some sort of sensor plate?

yes, exactly

A couple of thoughts.

1. Try adding a resistor in series with the input of the first gate to protect it against the over real voltage swings.

2. Although the current in the nets either side of the 40pF is the same, the voltages on either side are different. This means that there won't be much cancellation of the electric field around the cap.

If you look at the voltage at each end of the cap I think you'll find that the high frequency content is greater in your version of the oscillator than the standard RC+Schmitt oscillator.

Hi Andy
My real name is Denis (just in case you wonder).
Thank you so much for your help! I really appreciate it. I'm not sure how long I shall bother you, with minor boring stuff :(

About your thoughts:

1. Indeed there is still over voltage swings on probe "IN" in my design. So I added R4, but that doesn't help (no surprise: as R2 is already in series with the input)

2. I'm not sure I understand: So the electric field is bad? How would it be cancelled? You're saying the standard RC oscillator would be better (even if the cap would be connected to gnd and then act as an antenna?)

Hi Denis,

Please see:

https://easyeda.com/andyfierman/Ways_to_make_oscillators_using_logic_gates-a05d617ad010486183bec8831a7f9af4

2) I'm not sure I understand: So the electric field is bad? How would it be cancelled? You're saying the standard RC oscillator would be better (even if the cap would be connected to gnd and then act as an antenna?)

You need to understand a lot more about Design for EMC for an explanation to make much sense.

For simplicity, the single scmhitt trigger gate relaxation oscillator generates (almost) a triangle wave. This has a lot less high frequency harmonic energy than the sharp edged waveform in the standard 3 gate oscillator.

But you also have to decide how stable and reproducable you want the oscillator frequency to be.

:)