I need help regarding the Spice simulation
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Maxi Steiner 2 months ago
Hey Guys! I am currently building and simulating my first circuit. This one is my copy of the Moog 24dB/Octave Ladder Filter (Low Pass Filter) ![Circuit.png](//image.easyeda.com/pullimage/MX2yqcGmJS0dGl9tPXp9NV2wOCDtRCg9HlvgpyFv.png) Now, as you can see in my screenshot above, I placed two probes. One at the Output of OpAmp2 (volProbe8) and one right after them at the output of the last OpAmp (volProbe9). After runnung an AC analysis i get this chart: ![Waveforms.png](//image.easyeda.com/pullimage/taB6aI1hhjAov2vz0gsif8D7H5Mc6FOwh0xy9FzJ.png) Why is there such a decrease in Voltage between those two OpAmps? Is my PowerSource-Management false? Or are those OpAmp-models not functional in Spice? I am quite desperate right now.. Thanks for every kind of hint you can give me :) Greetings from Germany! Maxi
Comments
Maxi Steiner 2 months ago
I have just made my project public, so feel free to change it as you want. :)
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andyfierman 2 months ago
@maxisteiner57, Please  help people to help you by posting the url to your public project. I will look at your project and comment but as this seems to be your college project that you asked about in an earlier post, this is getting close to asking people to do your homework for you. Questions: Have you been through the Spice Tutorial? Have you run the examples in it? Have you tried setting up some dummy projects, much simpler than this project, to learn how to use the tool before launching into a complicated simulation like this? :)
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andyfierman 2 months ago
@maxisteiner57, As explained to you in: [https://easyeda.com/forum/topic/My-Circuit-does-not-work-in-Simulation-Mode-What-have-I-done-wrong-b66dd62884a543f78d8d6a50672295c0](https://easyeda.com/forum/topic/My-Circuit-does-not-work-in-Simulation-Mode-What-have-I-done-wrong-b66dd62884a543f78d8d6a50672295c0) this connection to the inputs of U2 does not work because they have nowhere to draw their input bias currents from. The required DC path is blocked by the series caps: ![image.png](//image.easyeda.com/pullimage/sep7TL3R80woIAUrTlIJtnCc8mXzuOrsVGxdEyWU.png) Read: [https://www.analog.com/media/en/training-seminars/tutorials/MT-038.pdf](https://www.analog.com/media/en/training-seminars/tutorials/MT-038.pdf) Pay particular attention to the last paragraph on page 1!
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andyfierman 2 months ago
@maxisteiner57, You have no net labels applied to the power supply rails therefore you have no connection to the V+ and V- nets everywhere else in your circuit. Therefore U2 is powered but none of the rest of the circuit is powered: ![image.png](//image.easyeda.com/pullimage/x6HD1kVXReT1Gt7JD9GaWMrG3lNsAexp7Ra56YB6.png) Export your LTspice netlist and check it: **File > Export Netlist > LTspice for this sheet...** You can connect things by wires or by net names or a mix of both but if there's no wire to it and no matching netname attached to it then it is not connected. Please refer to the **Simulation Tutorial: > Introduction to using a simulator > Avoiding Common Mistakes > Components are connected by netnames** in: [https://docs.easyeda.com/en/Simulation/Headings/index.html](https://docs.easyeda.com/en/Simulation/Headings/index.html)<br> <br>
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