Please give more details and some screenshots.

This was due to the error of the names of the nodes, when different nodes what must be connected to different ports were named the same. In this case, the name of the node in the PCB editor inherit the name of one of the ports. I do not insist that this is a program error, but it is preferable to understand for PCB tracing the name of the electrical node and not the port name. The screenshots show the system behavior before and after correcting the node naming error. I hope that my thoughts will be useful to you. Thank you very much. Before  error fixing of the naming   After error fixing of the naming  

Hi You placed a net port and net label on one wire, when convert to PCB, the editor only will take the first one to be the net name.

[https://docs.easyeda.com/en/Schematic/Wiring-Tools/index.html#Net-Label](https://docs.easyeda.com/en/Schematic/Wiring-Tools/index.html#Net-Label) 

Yes, my error of node naming led to this. The possibility to use synonyms is good and correct feature. But it is not clear which of the synonyms will be used in the PCB editor. Can I define a preferable name for PCB editor using?

As long as you make the port name (and voltage probe name in simulations) the same as the net label name then there is no problem. Names are case insensitive but please use only a-z, 0-9 and underscore characters in names. .

Thank you very much.