Hi marco.missyou, Welcome to EasyEDA. At present it is not possible to co-simulate using VHDL or Verilog files. You may like to have a look at: * It is possible to use 3rd party spice models for all sorts of devices. To use spice .model definitions in a schematic, please see: https://easyeda.com/file_view_Playing-with-model-parameters_Ev5rpnJG2.htm https://easyeda.com/file_view_N-channel-depletion-mode-MOSFET-using-a-.model-statement_NnhztL2kC.htm To use spice .subckt definitions in a schematic please see: https://easyeda.com/file_view_Attaching-a-.subckt-to-a-symbol-01_808qkCTN5.htm https://easyeda.com/file_view_Attaching-a-.subckt-to-a-symbol-02_6OkCwO5nF.htm