I wrote a post a while back about exactly this problem but I can't find it right now. IIRC, the basic idea was like this: Copy the trace, paste it outside the PCB then increase the width and convert it to a solid region set to no solid. Then move it back over the original trace. This will create a copper-free area around it.

This is it: [https://easyeda.com/forum/topic/How-to-create-a-four-wire-sensing-or-Kelvin-Connection-on-a-PCB-8034986947764c1fb1a872de020160e8](https://easyeda.com/forum/topic/How-to-create-a-four-wire-sensing-or-Kelvin-Connection-on-a-PCB-8034986947764c1fb1a872de020160e8) In: [https://easyeda.com/andyfierman/4-wire-sensing-using-the-kelvin-connection](https://easyeda.com/andyfierman/4-wire-sensing-using-the-kelvin-connection) have a look at the PCB layout: **Copper cleared using copper cutouts from copied and scaled Kelvin tracks** which has a description: _This is what happens after the HCP1 and HCP2 high current paths are surrounded by copper cutouts created by selecting and copying the original Kelvin connection tracks,  then increasing their widths, converting them to Solid Region "No Solid" regions and then placing them back so that they overlap the original track sections._

I don't know how familiar you are with the principles of Signal Integrity and I'm not clear from your screenshot quite how the rest of the tracking will work but beware of some potential SI gotchas. In HF circuits, the return current path follows the path of lowest impedance. This will be the path of least loop area because this will be the path of least inductance. The return path will therefore follow the path of the signal trace. Routing a track to cross a break in a ground (or power) plane causes the return current to have to follow a longer path around the break than the signal path across it and so creates an increased looped path for the current flow. That loop introduces an inductance (of around 6nH/cm) and causes the return path current to flow in areas where it would not otherwise and therefore potentially cause crosstalk in tracks that are not physically close to the track crossing the plane break if the displaced return path current then interferes with the return current of those other traces. 1. If the ground track is isolated from the rest of the ground plane and that plane extends under the device then that plane is still capacitively coupled to the device; 2. If the plane under the device is made into an island and included as part of the isolated ground under the device so that there is a moat all the way round the device except for the ground track which forms the drawbridge, then no tracks should cross the moat. The only way tracks should be routed to and from other pins on the device is along the path of the drawbridge. That avoids any signals or supplies crossing a plane break which as explained above is a source of crosstalk and therefore noise injection. 3. Even more risky would be to remove the plane under the device entirely because that in effect makes the moat into a lake that must not be crossed and so makes it almost impossible to route tracks to other pins without then leaving the area of their local ground return path of the drawbridge.

Thanks Andy. ...or, live with DRC errors :-) I have to anyway with a PCB antenna. EasyEDA team: consider allowing an IGNORE feature on some DRC errors. This would allow me to more easily know that I am not breaking rules somewhere I shouldn't.

In terms of layout, yeah, these are only for power pin decoupling and I'm keeping them short. No signal will cross them. I will have continuous ground on L2 besides, with plenty of continuous ground on L4, and as much ground on L1 and L3 (power) as possible, all stitched together.