"I need to find a way to connect AGND with GND on the bottom layer without getting a DRC error." **Short answer:** EasyEDA does not have a concept of different names being applied to the same net, which electrically is what you are trying to do. You can put different netnames on the same net but EasyEDA will only use (I think) the first one you apply to the net. The Design Manager will warn you about multiple net names. <br> **Long answer: ** Sorry but you have to accept that if two different nets are joined together by copper then they MUST have the same netname. So if you have two different nets and you then run a trace between them, both nets MUST then be assigned the same netname. This net name may be one of the two original names or it may be a thirds, new name but the whole of both original nets **will be** reassigned the same names. There is no realistic way that an EDA tool can deal with joining two traces by copper on a PCB other than by doing this because EDA tools only understand connectivity by netnames. If two nets have the same name then they are the same net. If they have different names then they are different nets and they are not connected together. Using solderable links can be made to work but you may have to create special small clearance design rules for nets with solderable gaps or ignore the DRC errors they may produce if you leave the normal clearances in place. You may also have to remove the soldermask between the two sides of the gap in order to ensure thay they are bridged by solder in the assembly process. If you want to add "jumpers" or shorting links then the most reliable way to do this is by adding 0R resistor links. Please see also: [https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6](https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6) [https://easyeda.com/andyfierman/shorting-link](https://easyeda.com/andyfierman/shorting-link) [https://easyeda.com/andyfierman/cuttable-link-demo](https://easyeda.com/andyfierman/cuttable-link-demo) 

Hello, also take a look at this video from Robert Feranec with Rick Hartley about GND in PCB layouts: [https://www.youtube.com/watch?v=vALt6Sd9vlY](https://www.youtube.com/watch?v=vALt6Sd9vlY) Very interesting subject.

Thanks a lot for your comments and andvise.

One way to handle different GNDs: [https://oshwlab.com/topirinkinen/thermocouple_esp](https://oshwlab.com/topirinkinen/thermocouple_esp)<br> <br> I connected GND and AGND together on one point only:  The result is two copper planes next to each other, and connected. Note that the connection is placed on purpose at opposite side of C7, to make the return current (from AGND to GND) loop area as small as possible.  -Topi

@topirinkinen, @jaha2002, As my posts about this subject explain, you can join two nets using a 2 pin symbol and a 2 pad footprint with overlapping copper like this:  but this is the DRC error that you get by doing that: 

Hi! Other way to join AGDN and digital GND is to use 0ohm resistor and let JLCPCB handle this problem in their SMT assembly. And just like my fellow countrymen Topi Rinkinen says that it needs to be placed on a strategic place where the return current loop area is in the most minimal. Regards, Markus Virtanen HW / Electronics Designer

Markus, I believe I am your citymen...

@jaha2002, @topirinkinen, @markus_jidoka, A bit of background. :) "...use 0ohm resistor...needs to be placed on a strategic place where the return current loop area is in the most minimal." The use of a plane separated from - and sometimes surrounded by -  but linked at one point to another plane on the same net is sometimes referred to as "Moat and Drawbridge" where the Moat is the gap and the Drawbridge is the link. There are occasions where using "Moat and Drawbridge" can appear to help but in my experience, this is usually only as a result of poor layout somewhere else. The problem with any split between two planes is that it forces all the return path current from any signals, including the power supply, passing between the two planes to have to pass through the drawbridge. To minimise the possibility of problems with: * EMC susceptibility; * EMC emissions;  * Signal Integrity (SI); * Power Integrity (PI) as you point out, the loop enclosed by the signal and the ground return paths must be minimised. In an ideal world, any traces passing between the two plane areas should therefore physically pass directly over the drawbridge and not over the moat. However, in the real world this is very hard to achieve successfully. All too often the rule is broken and traces end up crossing the moat or, because there are so many signals to pass over it, signal traces are so close and the return currents passing though the drawbridge are so bunched up that they generate significant crosstalk between the signals as a result. Widening the drawbridge reduces the bunching but in most cases this results in such a wide drawbridge that the two plane areas might as well be made into a single continuous plane. The problem with using a 0 Ohm link resistor is that this has to sit on an outer layer so any signal trace has to be on the opposite - or, on a multilayer PCB, an inner -  layer. If the planes are already on the same outer layer as in topirinkinen's example then that is not really a problem but if the planes are internal then the impedance of the additional vias required to connect the inner planes to the surface drawbridge resistor probably may cause cause more of a disruption in the ground return path current than isolating the area with a moat solves. It could be argued that placing C7 with one end connected to a possibly noisy +5V supply and the other end connected to what is supposed to be a quiet AGND somewhat defeats the object of placing the 3.3V regulator next to it across the moat there to try to produce a quiet 3.3V supply to the analogue side of the MAX31856. It might be better to ground C7 to the GND side of the plane. The way that U1 has been placed so that the plane split runs between the analogue and digital sides of the chip looks like the right thing to do but this also means that the AGND and DGND are then separated by a much longer and, because it passes through a width restriction of the drawbridge, a higher impedance path, than if they were on the same continuous plane. This may open the possibility of capacitive coupling of GND side noise through the device to the AGND side or that the point where the drawbridge is located may actually be noisier than where the DGND pin of the chip is connected to and so allowing the AGND connection to be noisier than if they were connected together on a continuous plane. Looking at Figures 4 and 5 in: [https://datasheets.maximintegrated.com/en/ds/MAX31856EVSYS.pdf](https://datasheets.maximintegrated.com/en/ds/MAX31856EVSYS.pdf)<br> <br> it is interesting to note that the MAX31856EVSYS board does not use a split ground: the whole of the circuit is over a single ground plane area. * That link from with @deskpro, to the video of Rick Hartley and Robert Feranec is excellent: well worth sticking with it for the whole hour and three minutes (or less if you can keep up with a faster playback). I was lucky enough to go on one of his courses a few years back during which, as part of a discussion with him, I created this simple little simulation of a discontinuity in a lossless 50R transmission line: [https://easyeda.com/editor#mode=sim,id=5ba8dcb605a34936983729f2f3e3776a](https://easyeda.com/editor#mode=sim,id=5ba8dcb605a34936983729f2f3e3776a) part of: [https://easyeda.com/andyfierman/Misc_simulations-lVd6oGYSa](https://easyeda.com/andyfierman/Misc_simulations-lVd6oGYSa),

@jaha2002, @topirinkinen, @markus_jidoka, For info: I raised a Feature Request about a net-splitter or net-tie back in February: [https://easyeda.com/forum/topic/Net-tie-a-copper-only-component-with-2-pads-to-split-nets-without-DRC-errors-and-multiple-netname-warnings-b6a099bf01bb4055b821ab398ee37b60](https://easyeda.com/forum/topic/Net-tie-a-copper-only-component-with-2-pads-to-split-nets-without-DRC-errors-and-multiple-netname-warnings-b6a099bf01bb4055b821ab398ee37b60) You could reply to it with "+1" to bump not up the ToDo list a bit. :)