Two points that might help. 1. In EasyEDA, the schematic is the master document. Therefore the EasyEDA Design Flow starts with all the information that is entered into the schematic, such as package assignments and net names, being transferred into the creation - and subsequent updating - of the PCB. So if you name/rename the nets in the schematic then those net names will be passed/updated into the PCB;  2. Anything that is on - or forms an integral part of the PCB - must be represented by a schematic symbol with an appropriate PCB footprint assigned to it in order for it to be correctly passed into the PCB. Therefore, if you have a special PCB structure such as your joining of two nets using a pad with two holes then you need to create a correcsponding symbol that has that footprint assigned to it. Then the footprint will not be overwritten when you update the PCB from the schematic.

Can you post some screenshots or a link to a public project to illustrate this issue?

I am doing exactly what you have suggested but that is what is throwing DRC errors. The component symbol name is `NetJumper` and the footprint name is `Lynx_NETCONNECT`. Below you can see a typical DRC error (Clearance) and I have selected the trace connecting to the Lynx_NETCONNECT footprint with the DRC error. You can see the trace does not overlap the footprint:  I assume you can examine the footprint yourself. If I there is a way to correct the footprint or if you have another alternative, I would love to hear it.

I'm assuming that you want to do this to make some sort of link that you can physically cut on the PCB to disconnect two tracks as some sort of select on test adjustment. Sorry but if the nets connected to each side of the link have different names then I cannot see a way to make this work. You have two pads with different numbers shorted by a piece of track. There is no net name that can be assigned to this track that matches both of the (different) netnames that will be connected to the pads so the DRC sees the track as a clearance error. The only way I can see to do what you appear to be trying to achieve - without using some sort of physical component such as a two pin header with a shorting link or a 0R resistor - is to make a footprint with a pair of pads very close to each other (which may then cause clearance errors due to their proximity anyway so a local clearance rule may have to be applied) and which you then selectively solder bridge during assembly and/or test. For example:  **If however, you accept that the netnames either side of the "link" MUST be the same then you can make a footprint with 3 pads all numbered as pin 1 like the cuttable link shown in this project:  ** [https://easyeda.com/andyfierman/cuttable-link-demo](https://easyeda.com/andyfierman/cuttable-link-demo) * However, please read the library Descriptions of the symbol and footprint for CUTTABLE LINK before use.

No, I am not trying to make a jumper connection. The reason for the different net names is to make the schematic more clear and prevent connection errors in the schematic. In trying to cite use cases for doing this, I began to realize that perhaps I should not be connecting different net names after all. So thanks for the help anyway, and I think I will adapt my practices to use only one net name per net.

Is there still no way to connect two different nets that have different names? Our (regular) use case: when the PCB is in production use, the link is closed. Only in development, we might need to cut the link. We typically place this link between two pins of a pin header so we could reconnect with a jumper.

"We typically place this link between two pins of a pin header so we could reconnect with a jumper." You've answered your own question because then it's two nets separated by a 2 pin header. One net on one side of the header. One net on the other. That's a non-issue. If you want a cuttable track then I have already described the solution to that option above: _If however, you accept that the netnames either side of the "link" MUST be the same then you can make a footprint with 3 pads all numbered as pin 1 like the cuttable link shown in this project: _ [https://easyeda.com/andyfierman/cuttable-link-demo](https://easyeda.com/andyfierman/cuttable-link-demo) * _However, please read the library Descriptions of the symbol and footprint for CUTTABLE LINK before use._

Thanks Andy The great thing about cuttable links is that they connect by default. The header is not populated for production PCBs, so there is no way to connect the nets with a jumper. Thus, it's not a solution. Will add 0R for now. The routing gets messier with 5 0R around the 10 pin headers but I guess it's best I can do in easyeda.

Without sight of your schematic I don't quite nderstand the rationale behind you need for headers/jumpers and 0R resistors but as long as you understand the options that's fine. I'm not sure if any other EDA tools understand having two different netnames on different secgemnt of the same net either in a schematic or in a PCB. The pins on Schematic Symbols or the pads on PCB Footprints are connected by netnames. No more, no less. The wires in schematic are somply a graphical convenience to make the schematic more (or in some cases, less!) human readable. The tracks ina PCB are a physical requirement for connectivity and a peice of copper that is joined to another has no knowledge of their having different names in different places: if they are connected they are by a very real physical definition, the same net.

totally agree with your last explanation. To give you an example of an open source tool, KiCad has "net tie"s for that. So you can connect two nets with different names directly with a copper trace (and not with a physical component like a 0R resistor). Attached 'R_short.jpg' from KiCad shows such a net tie for a R footprint. Those pads are rarely used, only when we need to slow down the rise time of a signal or/and want to change the impedance of a connection. It's easier and more reliable than cluttering boards with 0R.  The solution I described in the post above is for rewiring and measuring nets in development while having the same layout for production. The rewiring/measurement is very rarely used and it's way more important that the connection between the 2 nets is reliable. (In this particular case we also wouldn't have space for the header in the production case). In 'header.jpg', the green arrows mark those net ties/cuttable links (or however you want to call them). When we do this PCB in easyeda, we have to replace these net ties with 0R resistors for each connection what makes the layout messy but it works. 

Think I see the context now. You could create a cuttable link with the two (or more) suitably shaped pads having different numbers and then just ignore the DRC errors that will create. That will allow you to have different net names on either side of the link at the expense of having to remember which DRC errors it is safe to ignore. This appears to be how the KiCad "net tie" footprints are created. Do they not generate a DRC error?

yeah, ignoring DRC is an option. We have like 10 such net ties on a board and then it becomes hard to spot the real errors. But it's  certainly a second work around besides 0R. KiCad does not generate DRC errors: Net ties are in the standard library and if you adapt any of those footprints\, KiCad recognizes the net tie\. I \*guess\* there is hidden flag somewhere in the footprint? Thanks for your quick reply and support

just crossed my mind, when there are no net ties (or however called), how could e.g. an analog ground connected to a digital ground?

@padrone, It's the same problem. :) Although actually it is only a matter of labelling because again, physically they are the same net. It is only the PCB routing that makes them functionally separate. It might be a good idea ot explain this requirement carefully in a separate Feature Request and refer back to this post.

we prefer to do a careful layout and avoid separate AGND, so this use case of net ties is anyway low priority for us. Net ties/cuttable links/whatever_name for shorted headers or resistors has definitely a higher wish factor :-) thanks anyway for your work, easyeda does so many things better!

I would like to see net tie implemented. I'll try to explain another use case that is solved with net tie. Suppose that you have a big circuit with a voltage track and a gnd track that connects many components and a led strip. The led strip uses the same voltage track and GND track of the other components but since it absorb much more amps it needs a much wider track. How can you use autoroute in this situation? There is no way to say to easy EDA that the track must be fat for for the first part where the LEDs are connected and thinner on the second part When they only need to power the other components. This problem is generally solved with a net tie. Please implement the net tie. <br> <br>

+1 for the net tie. for the same reason mentioned above: **Schematic clarity** Let's say I have a voltage regulator with a feedback pin\. I want that feedback pin routed next to the forward trace and connected to the forward trace \*at the load\* which could be some distance away\. If the schematic just shorts the forward and feedback pins\, it will not convey that important layout point\. If however, I route two nets, namely forward and feedback and place a net tie next to the load, this will be understandable. What I use right now, is the same method as also mentioned above. And this throws DRC errors, which are a nuisance because they distract from actual errors.

+1 - sometimes in life, nets need to be connected

+1 for net ties to implement cuttable links better. At least JLCPCB has a few 0R in their basic parts. Even a 1206 (C17888) which is big enough to reliably unsolder if needed.

I raised a feature request about this some time ago: [https://easyeda.com/forum/topic/Net-tie-a-copper-only-component-with-2-pads-to-split-nets-without-DRC-errors-and-multiple-netname-warnings-b6a099bf01bb4055b821ab398ee37b60](https://easyeda.com/forum/topic/Net-tie-a-copper-only-component-with-2-pads-to-split-nets-without-DRC-errors-and-multiple-netname-warnings-b6a099bf01bb4055b821ab398ee37b60)

@tobalt The second time I found this page, it was almost exactly for your use case, routing a feedback loop to a buck converter (same network as VCC, but very different layout requirements).

There is a Short-Symbol in EasyEDA Pro but it looks like it is not yet a complete "Device": 

Also in EasyEDA Pro: