Hi Zoltan, I'm not sure why your footprint gives this error but if you delete the net name `GND` in the centre pad (pin 17) and then check the Design Manager, you will find that the `GND` Net error disappears. Even if you decide not to delete the net name, the vias will connect to the bottom layer OK. You can check this in the Gerbers. * One thing you should do is to change the name of your footprint `16QFN3X3 w/ 0.3mm vias` to `16QFN3X3 with 0.3mm vias` because the `/` character is not allowed in schematic symbol and PCB package names. If you try to update the PCB, you'll find it throws a `Package Error`. If you change the name and update the package in the schematic and then do an `Update PCB`, you'll find the PCB updates with no error. BTW, I have tried creating your package with the vias already in it but for reasons I do not understand yet, it does not make a connection to the ground flood on the bottom layer. I did create some pads that are on all layers and have vias through them which do connect to tracks and layers correctly. You could use them as the basis for a variant of your footprint but be aware that the pad on the bottom layer will connect to the bottom layer with heat shunt spokes. `6MMPAD` `8MMPAD` `10MMPAD` Lastly, since your PCB footprint does not actually have any vias in it and you have to add them once the footprint is placed in the PCB, you may want to rename the footprint to remove the `with 0.3mm vias` bit. :)

Hi Andy, I copied a 3x3 TQNF-16 package, which has 0.2 mm vias and wanted to replace it with 0.3mm ones. After a bit of messing around I ended up removing the vias from the footprint package. I had a look at your examples and it seems that if I set the pad (pin 17) to be on 'All' layer rather than 'TopLayer', the error disappears. Good call on the Gerber viewer - wouldn't have thought of that myself! Thanks again for the help! Cheers, Zoltan

Note that if the centre pad is on `All Layers` then the centre pad will be connected to the bottom layer by heatshunts or `Spokes` unless you set: `Pad Connections => Direct`. Whilst direct connections improve the heatsink effectiveness of the centre pad, by the same effect, it will be very difficult to make a reliable solder joint to the pad under the package (and to pin 10 of the connectors).

Wow, thanks for the even more information! So, what would you recommend? Connect the pad and bottom layer with vias and ignore the DRC error or set to pad to 'All' layers?

* Some questions about how you are going to assemble these boards: 1. By hand? 2. Using a hotplate and/or hot air tool? 3. Using a small oven? 4. Ask for the boards to be assembled for you by EasyEDA (i.e. have them delivered as a PCBA)? What I suggest: If (1) set the pad to `All layers` and then use Spokes. If (2) or (3) delete the netname of the pad and connect the pad and bottom layer with vias. This will avoid the DRC error. If (4) email support@easyeda.com and ask if they can do this and what they advise to do about the pads. * Caution: I understand why you may want to do this but it is not normally a good idea to put SMPS regulators or controllers onto breakout boards. SMPS circuits switch large currents with *very* fast egdes so having any traces longer and/or narrower than absolutely necessary is not a good plan. Remember that even if the switching frequency is relatively low, the edges are just as fast and it is dV/dT and dV/dT that causes all the trouble... :) Maxim do not seem to have good PCB layout guidelines for this part but if you look around their other parts or similar parts on other manufacturers' sites, you can find a lot of good advice. Here's a reasonable introduction: P21 'Laying Out the Printed Circuit Board' in http://www.onsemi.com/pub/Collateral/SMPSRM-D.PDF