**BUG**
Concise problem statement:
The logic levels out of A1 and A2 are (a) different and (b) not right for simple unloaded CMOS output levels.
The setup for these gates is not visible to the user.
It is not clear what supply voltage these gates are using internally.
Steps to reproduce bug:
1. Run transient sim and observe waveforms.
Results:
A1 has logic 0 = 0.7V, logic 1 = 3.5V
A2 has logic 0 = 0V and logic 1 = 1.75V (i.e. half of A1 logic high).
Expected results:
Same logic levels out of both A1 and A2
Url:
https://easyeda.com/file_view_How-to-use-logic-gates_Y8Ie82Vd7.htm
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