Hi Andy Yes, it is a known issue, we will improve this in the future.

Is it still unslolved? I have two different boards, with copper area in both boards, and only plots the copper in the first board. Second one only shows the perimeter of the copper area.

If these are two different PCBs in separate files (i.e. they open in separate PCB Editor windows) then check the Copper Area Visibility setting in each of the PCB Editor windows. This is a PCB Editor canvas attribute setting which affects all copper areas in that canvas but can be different between separate PCB Editor canvases within the same Project.

Note that the question you have asked is unrelated to the subject of this post. If you wish to raise your issue as a Bug Report, please do so by posting a new bug report. Thanks.

That's what I have. Two boards (with 2 boards outline). The message I get is "EasyEDA does not allow inner board outlines to form cut-outs, please use SolidRegion or Hole". Is it the same problem ? 

So you have 2 PCB layouts in the same PCB file? In that case it looks like the problem is the same as I first posted about and that it has not yet been resolved. However, if you put 2 PCB designs into the same physical PCB layout then you will be charged for 2 PCB designs. In which case why not submit them as separate PCBs anyway? Also, the way you have put the two boards so close together, how are you going to separate them? You might be better to lay them out for a V-cut between them. Have a look at the JLCPCB site for the design rules for V-cut. Or are you doing this as a single board to make assembly easier in some way?

Yes, but there is a problem. One board (the board inferior) is shorter than the above, so I have added a vertical hole to be routed on the board. This is not possible on the web. Also, when I works, I will add a rail border, fiducials, etc... So in that case, should I export the files and import in another PCB editor to complete the pannel correctly? thanks in advance

The hole is the long grey strip to the left of the LEDs at the left hand end of the lower board? I get the idea of the routed hole to break apart the PCB but I don't understand what you mean by: "This is not possible on the web." You also said: "... I will add a rail border, fiducials, etc..." Please refer to: [https://jlcpcb.com/capabilities/Capabilities](https://jlcpcb.com/capabilities/Capabilities) "So in that case, should I export the files and import in another PCB editor to complete the pannel correctly?" Why? If you do your PCB as two separate boards as I suggested above then it is easy to get EasyEDA to panelise each design: [https://jlcpcb.com/quote/pcbOrderFaq/Panel%20by%20JLCPCB](https://jlcpcb.com/quote/pcbOrderFaq/Panel%20by%20JLCPCB) It means you get two panels. One panel of one PCB design and another with the other PCB design. They are easier to V-cut and separate as there is no need for the routed slot and any post-separation work to clean up the snapped apart edges Suggest you ask support @ JLCPCB.com for advice about how to do your own panellised PCBs Obviously I don't know why you want to do the design this way but from here it looks like you are making extra work and expense for yourself. :)

Hello andyfierman. That's because the panel is going to production and both boards will be produced at the same time, because both boards are part of the same electronical device (one stencil for the device means not to change and program the stencil machine each time they change the board), and also they don't need to change the program of the PNP. Refering to "This is not possible on the web.", I meant to add two boards of different size in the same panel. At least I wasn't able to find how to do this in the JLCPCB web. I haven added the fiducials, edge rail, etc, because I wasn't able to join properly both boards, so I stoped with the panel design on EasyEDA. My idea was to create the panel layout directly in EasyEDA to ensure this is produced in the way I want. Thanks in advance

OK, I understand. I think if you do your design as you have so far but allow for a V-cut on the long edge between the two boards to separate them lengthways and then use the routed slot to remove the unwanted left hand end of the shorter board then you maybe able to get EasyEDA to panelise the two boards as a single PCB. I'm not anexpert on this part of the EasyEDA PCB process so you're probably better to ask support at EasyEDA and JLCPCB directly. Just be clear about what you you would like them to do and why.

@andyfierman The problem is that the copper area (GND area) on the board below, is not filled, so I can not export gerber from EasyEDA.

Try making the two board outlines out of two separate rectangles and moving the long sides very slightly apart so that they do not overlap. You have to do this to allow for the V-cut anyway.

@warloofer For this error message, please ignore it and keep going to generate the Gerber. At v5.7.x, we will provide the panelize function for PCB self-panel.

@warloofer, You can check your Gerbers using gerbv: [http://gerbv.geda-project.org/](http://gerbv.geda-project.org/)