From topics like those listed below, it is clear that a component is needed which can split a net into two separate nets in the same way as a 0 Ohm resistor or a series component as part of an impedance matching network but which is in fact just made of copper.
[https://easyeda.com/forum/topic/How-to-design-a-PCB-Lib-for-a-PCB-Antenna-efa50ba1cdd9433c958ceedbad520398](https://easyeda.com/forum/topic/How-to-design-a-PCB-Lib-for-a-PCB-Antenna-efa50ba1cdd9433c958ceedbad520398)<br>
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[https://easyeda.com/forum/topic/Inconsistent-connection-to-pad-on-single-numbered-multi-padded-footprint-40071cd5cf5a478cac7be7d4334a02a1](https://easyeda.com/forum/topic/Inconsistent-connection-to-pad-on-single-numbered-multi-padded-footprint-40071cd5cf5a478cac7be7d4334a02a1)<br>
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[https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6](https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6)<br>
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[https://easyeda.com/forum/topic/Non-exposed-coper-vias-in-footprints-341192f38fb04a1b8addae2065ba400c](https://easyeda.com/forum/topic/Non-exposed-coper-vias-in-footprints-341192f38fb04a1b8addae2065ba400c)<br>
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At the moment a 0 Ohms resistor or a series component as part of an impedance matching network works OK because it has two separately numbered pads that are not connected in the Footprint by copper.
However, any attempt to replace that with a copper element:
1. results in warnings about more than one name on a net and;
2. generates DRC errors.
What is required is a footprint which has two separately numbered pads that is joined by a copper element BUT for which:
* no warnings are given about multiple netnames and;
* DRC errors are not generated flagged
Apparently there is such a component in Kicad called a "net-tie".
A net-tie in EasyEDA would solve a lot of problems in things like connecting to PCB antennas and splitting ground areas.
Such an element would have to have a parameterised width to match trace widths into which it is inserted and a parameterised distance between the two pads.
The net-tie element would:
1. be a single layer element only. There is no need for it to be a multilayer element;
2. be possible to place onto **any** layer;
3. have to have a parameterised width to match trace widths into which it is inserted and;
4. have to have a parameterised distance between the two pads;
5. work with traces, solid regions and copper Areas;
6. if possible work inside a PCB Footprint (a.k.a. PCB Lib).
