Net-tie: a copper only component with 2 pads to split nets without DRC errors and multiple netname warnings.
510 8
andyfierman 7 months ago
From topics like this, it is clear that a component is needed which can split a net into two separate nets in the same way as a 0 Ohm resistor or a series component as part of an impedance matching network but which is in fact just made of copper. [https://easyeda.com/forum/topic/How-to-design-a-PCB-Lib-for-a-PCB-Antenna-efa50ba1cdd9433c958ceedbad520398](https://easyeda.com/forum/topic/How-to-design-a-PCB-Lib-for-a-PCB-Antenna-efa50ba1cdd9433c958ceedbad520398) [https://easyeda.com/forum/topic/Inconsistent-connection-to-pad-on-single-numbered-multi-padded-footprint-40071cd5cf5a478cac7be7d4334a02a1](https://easyeda.com/forum/topic/Inconsistent-connection-to-pad-on-single-numbered-multi-padded-footprint-40071cd5cf5a478cac7be7d4334a02a1) [https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6](https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6) [https://easyeda.com/forum/topic/Non-exposed-coper-vias-in-footprints-341192f38fb04a1b8addae2065ba400c](https://easyeda.com/forum/topic/Non-exposed-coper-vias-in-footprints-341192f38fb04a1b8addae2065ba400c)<br> <br> At the moment a 0 Ohms resistor or a series component as part of an impedance matching network works OK because it has two separately numbered pads that are not connected in the Footprint by copper. However, any attempt to replace that with a copper element: 1. results in warnings about more than one name on a net and;  2. generates DRC errors. What is required is a footprint which has two separately numbered pads that is joined by a copper element BUT for which: * no warnings are given about multiple netnames and;  * DRC errors are not generated flagged Apparently there is such a component  in Kicad called a "net-tie". A net-tie in EasyEDA would solve a lot of problems in things like connecting to PCB antennas and splitting ground areas. Such an element would have to have a parameterised width to match trace widths into which it is inserted and a parameterised distance between the two pads. The net-tie element would: 1. be a single layer element only. There is no need for it to be a multilayer element;  2. be possible to place onto **any** layer;  3. have to have a parameterised width to match trace widths into which it is inserted and;  4. have to have a parameterised distance between the two pads;  5. work with traces, solid regions and copper Areas;  6. if possible work inside a PCB Footprint (a.k.a. PCB Lib).
Comments
MikeDB 7 months ago
SECONDED !!!!
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peter_uk 5 months ago
+1 This would be really helpful in a lot of circumstanes.
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sblant 2 months ago
+1 here, please add a net tie!!!
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andyfierman 2 months ago
A really nice additional feature of a net-tie would be if it were possible to make it an adjustable shape so that it could form the tapered section between two different track widths. Making so that it could be angled or even smoothly curved would make it even more useful. :)
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tobalt 2 months ago
+1 for the net tie. for the same reason mentioned above: **Schematic clarity** Let's say I have a voltage regulator with a feedback pin\. I want that feedback pin routed next to the forward trace and connected to the forward trace \*at the load\* which could be some distance away\. If the schematic just shorts the forward and feedback pins\, it will not convey that important layout point\. If however, I route two nets, namely forward and feedback and place a net tie next to the load, this will be understandable. What I use right now, is the same method as also mentioned above. And this throws DRC errors, which are a nuisance because they distract from actual errors. A net tie would basically be simply a copper trace that ignores clearence design rules.
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tobalt 2 months ago
Other implementation suggestion that seem compatible with the way things are currently handled: \- Things with a blank net name or a specific netname e\.g\. NODRC\, ignore the clearence rules\. That way one could also use solid regions\, and traces as net ties\.\. \- Add another possible behavior of solid regions\, namely "Net Tie"\. That way it would behave like Solid but ignore clearence\.
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andyfierman 2 months ago
For clarity: For schematic use, a net-tie can be a simple 2 pin symbol such as a 0R resistor, to which the net-tie Footprint can be assigned.
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Xenons 1 month ago
+1 When? Hope soon as DRC errors or multiple net's get's messy.
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