* This is due to the same bug as you have identified in your earlier post: https://easyeda.com/forum/topic/Update_connection_lines_after_routing-z3DdywSQc When you press `Update PCB...` from the Schematic Editor or `Import Changes...` from the PCB Editor, then the changes to the schematic *should* be passed into the PCB exactly as you would expect.

In the earlier version, when you place a component at a wire, its net name will change,and if you update to PCB, the tracks and net name will be change too. but since this verison, that problem is fixed, but the earlier PCB tracks and net name we can't keep the same as before, you better use the `Convert to PCB` rather than `Update PCB`.

"you better use the Convert to PCB rather than Update PCB." That's really not helpful at all, convert to PCB means to redesign the whole thing. Is this going to be fixed in the next version?

When you design a PCB directly... Not using the schematics you get the same issues. whats more every time I cut and pastes I also get the same issues, on the new pasted objects The questions is do we need to fix it ? When you generate the artwork of the PCB, this still shows all the tracks correctly... and still links everything together correctly, or at least they do in the artwork images.

Designing a PCB directly, without a schematic is possible in EasyEDA but it is not our recommended workflow. Please see the Design Workflow in the Tutorial. Please also check that you are running the latest version of EasyEDA (V4.10.3 or later)

In normal circumstances i would agree with you, going forward this i will probably start with the schematics first.... But I was designing a board to fit in with another board... So component placement was important and quicker... Having said that.. You have not answered the questions from the thread above. Do we need to worry about NETs and and Errors when that artwork looks ok ?

@stengram, * You should always run the Design Manager before you submit a PCB for Fabrication Output. This will tell you about any unconnected nets and DRC Errors. (Note however that it cannot tell you about any incorrectly connected nets, which is another reason why it is better to start with a schematic because this gives you a clearer view of the desired connectivity and effectively acts as a second opinion in the even of a mistake.) * All errors should be corrected before you submit a PCB for Fabrication Output. In other words, boards should not be submitted with errors. Whilst you may be able to verify the connectivity of a simple PCB by eye by looking at the Gerbers, you should not rely on this approach for complex PCBs.

I agree with the original poster's point: I encountered the same behaviour and I also interpret this as a bug, or at least missing functionality: Suppose there's an existing schematic connection for which I change the net name, \- If there are already correctly routed PCB traces using the old net name \- And the new net name does not coincide with any other already existing net name I would see no danger to rename/relink all already existing PCB traces to the new net name - or at least ask the user whether he/she would like the PCB traces also relinked. With the current behaviour, I feel like I have no possibility to change a net name once I've started creating the PCB because I have to reroute all PCB traces. Effectively, this is caused by a couple of issues that play wrong together: 1) The issue as described by the original poster (renaming doesn't cause an update of PCB traces) 2\) Whenever I add a net label to multiple connections in the schematic\, the default label \_stays the same\_\. This would immediately clash when updating the PCB nets automatically \(since they would be joined in a single net\, which is not the goal\)\. 3) I can't seem to find a UI function to relink currently existing PCB traces to a different net - other than selecting a single trace, and typing it into the Net property. The issue here is that when small traces are present on a pad, they can't be individually selected anymore (since you always select the pad). If I would use the "Nets" menu in Design Manager, I have no possibility to rename/relink it. A solution for 1) I have posted above A solution for 2) would be to automatically update the newer net labels with _1, _2, _3, etc. whenever you place newer ones, or to ask the user if he/she would really want to join multiple nets (and if not, provide the ability to rename) A solution for 3) would be to provide an additional "relink/rename" option for a given net in the Design Manager menu For the moment, I feel that changing the net label in schematic view horribly breaks the PCB design (when importing changes) causing a lot of additional rework time and frustration. On the other hand, if I overlooked a UI function that actually does this - please let me know (and perhaps making it more prominently visible in the UI also helps other users).

Hi, I have a common problem with designing PCBs and NETs changing name. If you have a working Schematic and PCB. Now: Lets say you need to change a component and its footprint, because a component is out of production. You replace the component, which is pin compatible, but the footprint has different spacing. Now when you update the PCB, the footprint is replaced with a slightly larger footprint, and then all nets now touchiing the updated footprint, change name somehow. This is NOT wanted. The schematic connections has not changed at all, except some component is replaced with a different part and the footprint is changed accordingly. No nets have changed, but the PCB update mixes up nets, just because wires that could be there before, now happen to touch the new pads during the update.

@maximumiq, Can you post an example project or at least a couple of screenshots to clearly illustrate this situation? Your images need to clearly show the net names, pad numbers and any ratlines before and after the change.

@maximumiq Right-click the track, select - select connection, change the net name at the right-hand panel. there is because of supporting update the track net, such as, when VCC update to VEE. it will has some situation can not dealing very well, even the old version.

Hi, We've experimented to make some examples, but had difficulties to recreate the actual problem because we didnt do exactly what had happened with original problem. Eventually we reloaded the project where we saw the problem last, and played the moves again that caused the problem. Now we understand the nature of the problem. On our Schematic, we replaced the footprint of a number of 16 pin SMD's, since the components had to change to another manufaturer with other demands in footprint details. The pin assignments are the same but the pads are a tiny bit different. So we selected another footprint to fit the new components specs. But in this case, the new footprint has a different attachment point, and thus is placed very differently (offset) when replacing the old footprint. And this is where some pins now lands perfectly on top of already exiting tracks going through that area. The PCB replace algorithm accepts, that if a track and a new pin is aligned perfectly, then the net for that track should change. In this case, the track's name will change to something matching the new footprints pad name. We made a screen recording video of it.

@maximumiq, Please post your video to UserSupport or convert it to animated gif to post here in the forum.

Here you have it. That was a lot of work ! 

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