You need to use EasyEDA editor to create some projects before publishing
No Ratlines
219 5
geoff2808 1 year ago
![N0Ratlines.png](//image.easyeda.com/pullimage/FQATB9PxJoKjVdeFSFT9fL54MlXj7oJuDnhOl2eS.png)Suddenly while drawing wires on the new pcb all the ratlines have disappeared and I can't get them back. How can I recover them?
Comments
andyfierman 1 year ago
Try Saving then reloading the PCB file. Maybe close and reopen EasyEDA.
Reply
andyfierman 1 year ago
See: [https://easyeda.com/forum/topic/Silk-layers-and-holes-are-locked-8f882fbe3eb74b16b93a173c23b29a57](https://easyeda.com/forum/topic/Silk-layers-and-holes-are-locked-8f882fbe3eb74b16b93a173c23b29a57) and check the ticks in the Layers and Objects palette.
Reply
UserSupport 1 year ago
disable it ![image.png](//image.easyeda.com/pullimage/xG8mamrLIP5sgzIoKpHt0Xq8ihUoDnQUOuAqQ6aa.png)
Reply
geoff2808 1 year ago
@usersupport Thank you. Perfect. Problem solved. I just ticked the empty box.
Reply
geoff2808 1 year ago
@andyfierman Thank you for your comment. Problem fixed. See my reply to @usersupport.
Reply
Login or Register to add a comment
goToTop
你现在访问的是EasyEDA海外版,建议访问速度更快的国内版 https://lceda.cn(需要重新注册)
如果需要转移工程请在个人中心 - 工程 - 工程高级设置 - 下载工程,下载后在https://lceda.cn/editor 打开保存即可。
有问题联系QQ 3001956291 不再提醒
svg-battery svg-battery-wifi svg-books svg-more svg-paste svg-pencil svg-plant svg-ruler svg-share svg-user svg-logo-cn svg-double-arrow -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus-@1x -mockplus-

Cookie Notice

Our website uses essential cookies to help us ensure that it is working as expected, and uses optional analytics cookies to offer you a better browsing experience. To find out more, read our Cookie Notice