Please illustrate an example of why you might want non-exposed copper in a pad, which is, by definition, exposed copper. You can cover a pad with solder mask by setting a **negative** solder mask offset equal to or slightly greater than the smallest dimension of the pad that you wish to cover. Check the result carefully if the pad is an irregular shape. Also bear in mind that, particularly if this is a surface mount pad, the paste mask will also have to be adjusted in a similar way to remove paste from the covered area. Note that holes in areas with non-exposed copper will not be tented by solder mask.

I don't want them to be pads. Generally, I want them to be vias. Consider the following: [https://easyeda.com/component/a91e4959524c4400bf527e26e3e5bf4b](https://easyeda.com/component/a91e4959524c4400bf527e26e3e5bf4b) note the "pad" on the inside of the antenna should just be a via. No exposed copper. Thanks for the info about the negative solder mask. Is there a way to do that to only one side? There are also some parts that should have exposed copper on top, but not on bottom. For instance, consider the TPSM53603 footprint: [https://easyeda.com/component/19f5833f42af4589b6b1a7ddac2f94a1](https://easyeda.com/component/19f5833f42af4589b6b1a7ddac2f94a1)

@andyfierman any ideas?

Hey folks, still looking for an answer here. Thanks!!

@bryan_6020 You can just open a regular PCB, place a via, copy it, and paste it in your footprint. Seems to work fine.

"I don't want them to be pads. Generally, I want them to be vias. Consider the following: [https://easyeda.com/component/a91e4959524c4400bf527e26e3e5bf4b](https://easyeda.com/component/a91e4959524c4400bf527e26e3e5bf4b) note the "pad" on the inside of the antenna should just be a via. No exposed copper." You can replace the pads with vias but you then have to temporarily set **Routing Conflict > Ignore** to connect to them and put up with the DRC errors that will generate. Or you can try the tricks below to close off the Solder Mask to the Multilayer pads. EasyEDA has no concept of a netname-splitting short-circuit element so PCB antennas in EasyEDA are horrible to deal with but this particular footprint is a nightmare: it will generate many DRC errors anyway because the spiral is constructed on track not pads and there are three pads each with different numbers whereas if the whole thing is made of pads and they are all given the same number then the footprint is at least consistent with this topic: [https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6](https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6) and you only have to deal with making the antenna conections so that they have the same netnames. If you have an antenna matching (RF) pad or network then that is not usually a problem although it might look a little odd in the schematic as the antenna port of the matching network will probably have to be named ground. See also: [https://easyeda.com/forum/topic/How-to-design-a-PCB-Lib-for-a-PCB-Antenna-efa50ba1cdd9433c958ceedbad520398](https://easyeda.com/forum/topic/How-to-design-a-PCB-Lib-for-a-PCB-Antenna-efa50ba1cdd9433c958ceedbad520398) [https://easyeda.com/forum/topic/Weird-Pad-Behavior-Traces-Not-Connecting-Properly-4660a264d69843b99ed5d5c735da4a96](https://easyeda.com/forum/topic/Weird-Pad-Behavior-Traces-Not-Connecting-Properly-4660a264d69843b99ed5d5c735da4a96) [https://easyeda.com/forum/topic/Cannot-get-antennas-pad-to-connect-to-any-track-2019598319464657b86a6bc0837d97a3](https://easyeda.com/forum/topic/Cannot-get-antennas-pad-to-connect-to-any-track-2019598319464657b86a6bc0837d97a3)<br> <br> "Thanks for the info about the negative solder mask. Is there a way to do that to only one side? There are also some parts that should have exposed copper on top, but not on bottom. For instance, consider the TPSM53603 footprint: [https://easyeda.com/component/19f5833f42af4589b6b1a7ddac2f94a1](https://easyeda.com/component/19f5833f42af4589b6b1a7ddac2f94a1)" The Solder Mask Expansion affects the top and bottom layers of a multilayer pad the same way. One way I can think of to work around that would be to place a bottom layer SMD pad over the multilayer pads and use the **Format > Bring To Front** option then close off the Solder Mask aperture for that bottom layer pad. Even so I am not sure that will work: you would have to check the Gerbers using gerbv. You may be able to do it the other way round. Shut the Solder Mask apertures of the Bottom Layer SMD and the Multilayer pads and then place round Top Layer SMD pads over the Multilayer pads to open the SolderMask on the top layer only. Again, check the Gerbers.

@andyfierman : "Please illustrate an example of why you might want non-exposed copper in a pad, which is, by definition, exposed copper." E.g.: Thermal vias in an exposed pad area, where the backside of the PCB should not have the via exposed. As the negative Solder Mask margin doesn't work for top and bottom side separately, the only way is to place unexposed vias into exposed top side pads.

@tobalt, Sorry but your comment "As the negative Solder Mask margin doesn't work for top and bottom side separately, the only way is to place unexposed vias into exposed top side pads." does not represent the only possible solution. @bryan_6020, @andreasbernhofer, The topic below shows: [How to remove the exposed copper (close the solder mask aperture) in a through hole pad](https://easyeda.com/forum/topic/How-to-remove-the-exposed-copper-close-the-solder-maks-aperture-in-a-through-hole-pad-5673aa46a6a34172ae2ad9ade57aaa87)<br> <br> and is added to: [https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1](https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1)<br> <br>

@andyfierman why would you add a pad where you actually just want a via? placing a pad as via will allow you to connect tracks to it - which is actually not desired on a design like the NFC coil posted by @bryan_6020 You sould be able to add regular vias to a footprint. It's already possible with Copy and Paste. I've made an example here: [https://easyeda.com/components/TEST-ROUND_4543334abce3475f8a8a34c4f89afdf8](https://easyeda.com/components/TEST-ROUND_4543334abce3475f8a8a34c4f89afdf8) 

@andreasbernhofer You can add vias to a footprint but they generate DRC errors. That's what this topic is about: [https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1](https://easyeda.com/forum/topic/How-to-place-multiple-vias-in-a-PCB-footprint-a34cf68d58414138898a56de60abd8c1)

Hmm, I don't get DRC errors for the via, but I get DRC errors for the tracks that are connected to the pad as part of the footprint 🤔  Tried the same without the via, just a track between two pads (a fuse) and I also get the DRC errors for the track.

@andreasbernhofer, You get DRC errors if you put any copper in a Footprint that is not made using pads: [https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6](https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6)

@andyfierman okay, got it. But this makes it literally impossible to create an NFC coil (or pcb resistor/fuse/antenna) footprint regardless of the VIA. A NFC coil footprint must have two pads with different numbers and one track (which might be a pad or not, this is not relevant) connecting them. When connected in circuit, both pads are attached to different nets. The NFC coil can be assigned one of the two nets, but it cannot be both nets at the same time. So the NFC coil will always generate a DRC error at one of its pads, you cannot avoid this. Keeping this in mind, I don't see why one would create the track of the NFC coil or the VIA needed as PAD. It won't eliminate all DRC errors and it introduces other complexities (like solder/paste mask) and unwanted behavior (like the ability to connect a track to the track/via). 

"You can replace the pads with vias" Dood. How?? In the PCB footprint editor, there is literally no "via" tool that i can find: 

Ah, i just re-read your post and saw that they have to be copied in. So i got them working:  Though after going through the rabbit hole of posts, it sounds like this is the incorrect way to do thermal pads, but rather i should be following the [instructions here]([https://easyeda.com/forum/topic/How-to-remove-the-exposed-copper-close-the-solder-maks-aperture-in-a-through-hole-pad-5673aa46a6a34172ae2ad9ade57aaa87](https://easyeda.com/forum/topic/How-to-remove-the-exposed-copper-close-the-solder-maks-aperture-in-a-through-hole-pad-5673aa46a6a34172ae2ad9ade57aaa87))?

@andreasbernhofer, "... this makes it literally impossible to create an NFC coil (or pcb resistor/fuse/antenna) footprint regardless of the VIA." Not if you follow the guidelines in the various links in my comments above. "A NFC coil footprint must have two pads with different numbers and one track (which might be a pad or not, this is not relevant) connecting them." There is no reason why the pads have to have different numbers. "When connected in circuit, both pads are attached to different nets. The NFC coil can be assigned one of the two nets, but it cannot be both nets at the same time. So the NFC coil will always generate a DRC error at one of its pads, you cannot avoid this." If a Footprint for the antenna shape is made where the antenna "track" is made as (or converted into) a pad and the antenna connection points also have pads overlaid on them all with the same number then, apart from: 1. the netname of the track connecting to the "FEED" port of the antenna must have the same (and therefore sometimes a bit misleading) as that of the "GND" end, which is a non-issue if you have a matching network or introduce a zero ohm link SMD resistor; 2. it being a little tricky to connect the tracks to the right snap points; you can connect to a PCB antenna with no DRC errors and you have complete control over the copper exposure/coverage of the whole of the footprint. Please take a little time to study my comments and the links I have posted in this topic. The video below shows how to make the connections to an example PCB antenna. Please note the Design Manager DRC check showing no DRC errors.  Please note carefully the technique use to make the two connections as other, more direct approaches will result in the behaviour seen in the bug report below: [https://easyeda.com/forum/topic/Inconsistent-connection-to-pad-on-single-numbered-multi-padded-footprint-40071cd5cf5a478cac7be7d4334a02a1](https://easyeda.com/forum/topic/Inconsistent-connection-to-pad-on-single-numbered-multi-padded-footprint-40071cd5cf5a478cac7be7d4334a02a1) The issues around PCB Antennas have not been fully resolved (and it is not within my power to do so) but my procedure does result in a way to make a connectable, DRC error-free PCB Antenna.

@bryan_6020, This topic (my original post, not the ones under it): [https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6](https://easyeda.com/forum/topic/How-to-avoid-DRC-errors-when-connecting-to-PCB-Footprints-a-k-a-PCB-Libs-90bf944fe3644b21a7d27a9e9d8df8d6) which also points to how to add thermal or electrical vias in a footprint covers everything  you need to know to answer your original question. My post above in reply to andreasbernhofer, extends the procedures to dealing with PCB antennas which you may find helpful but is not directly relevant to your original question.

@andyfierman okay sure, when you assign the same pad number it works, since all become the same net. But it still feels wrong to assign the same net to both ends of e.g. a resistor or coil. In the end, these are all workarounds.

@andreasbernhofer, As I said earlier: "EasyEDA has no concept of a netname-splitting short-circuit element so PCB antennas in EasyEDA are horrible to deal with " Unfortunately, I am not one of the software developers of EasyEDA so it is not within my gift to fix this and various other situations or apparent shortcoming in the tools. I can however offer help and advice and attempt to find ways to do things that maybe the developers haven't thought may be needed or are unusual uses for the tool. As you can see I have posted a number of Bug Reports to point out what needs to be changed and How Tos to describe how to deal with the situations covered by this and many other related topics but until such a component is introduced or a number of changes are made to the way copper elements in Footprints are defined and behave with respect to DRC then the procedure I have described should be seen less as a workaround and more as simply the way such things are done in EasyEDA. If you have experience of other EDA tools that offer simpler solutions to the problems or issues discussed in this or other topics, then you would be most welcome to present suggestions for solutions based on them perhaps as Feature Requests or Bug Reports or directly by contact with  EasyEDA support.

@AndyFierman. Thanks for your answers, and patience!

@bryan_6020, Thank you. :)

Still very confused about this. I looked at [your post]([https://easyeda.com/forum/topic/How-to-remove-the-exposed-copper-close-the-solder-maks-aperture-in-a-through-hole-pad-5673aa46a6a34172ae2ad9ade57aaa87](https://easyeda.com/forum/topic/How-to-remove-the-exposed-copper-close-the-solder-maks-aperture-in-a-through-hole-pad-5673aa46a6a34172ae2ad9ade57aaa87)) and your [example footprint]([https://easyeda.com/editor#id=!e48971ab94364709a723a6a1c310cefe](https://easyeda.com/editor#id=!e48971ab94364709a723a6a1c310cefe)). Per the instructions\, I added pads to the bottom layer that have an \*\*Solder Mask Expansion\*\* of \`diameter \* 0\.55\`:  I saved the footprint\, updated the part in my PCB design and then exported the gerbers to check them\. Looking at the \`Gerber\_BottomSolderMaskLayer\.GBS\` file I still see the cutouts:  Also\, looking at your sample footprint\, I don't actually see any pads on top or bottom that have the \`diameter \* 0\.55\` solder mask\. I dragged the various parts around and just see a normal pad and then some through\-hole/multi\-layer pads\, though those through\-hole pads do have the extended solder mask:  Anyone know what i'm missing here?

The bottom layer pad has a solder and paste mask extension of 5mm...  Please try going through the steps in: [https://easyeda.com/forum/topic/How-to-remove-the-exposed-copper-close-the-solder-maks-aperture-in-a-through-hole-pad-5673aa46a6a34172ae2ad9ade57aaa87](https://easyeda.com/forum/topic/How-to-remove-the-exposed-copper-close-the-solder-maks-aperture-in-a-through-hole-pad-5673aa46a6a34172ae2ad9ade57aaa87) again. I was a bit sloppy with my use of exactly -0.55 * the dimension so I have added the phrase "at least" to my topic.

Sorry: "The bottom layer pad has a solder and paste mask extension of **-5.000mm**..."

@bryan_6020 I may be way off base here but going back to your [relatively short and simple] question, 'How do I create a via in a footprint?', I'm not sure why your second question, 'Should I just set the solder mask to the radius of the pad or something?', isn't a viable solution. _ As an example I edited a standard SOT-23 footprint to include three 'pads', on the Multi-Layer layer. Each 'pad' has 'Solder Mask' set to -10mm. _  _ This footprint is then saved, and assigned to the part in the schematic. The PCB is created, the part has the new footprint and for comparison three actual 'vias' are added to the board. These are only edited to be the same size as the 'pads'. _  _ The result is this... _  _ Now.....unless I'm missing something there is no difference between the 'pads' in the footprint and the real 'vias', no exposed copper on any of them.....so this satisfies the question.....doesn't it? I'm sure you've already got to this point anyway so its confusing as to why this still isn't the answer. _ The only other thing I can think of is that you want 'Tented Vias', which I don't believe are supported by EasyEDA. _ Sorry if i'm totally wrong here, just trying to make sense of it all. _ Regards.

@mrtom528, @bryan_6020, I think that the subtlety in Bryan's question is that he wants the "via"pads in the Footprint and the top layer pad surrounding them to have exposed copper but the heat sink pad and the annulii of the "via" pads on the bottom layer to be covered in soldermask. The soldermask on the bottom layer should then look just like any other copper track or area with a via through it: covered but not tented.

@andyfierman, Ahhhh, right, gotcha.....so more like this then? _   _ Regards.

Andy is correct. I'm still unable to get it to work though. I see now that there a bottom pad for the entire area (it may just be me, but it's not clear from the step by step by instructions that's needed), and that it has it's solder mask set to `-5`, so i did similar on [this part](https://easyeda.com/components/QFN48G-0-5-7X7MM-FOR-TOSHIBA-TB67H420FTG_2095c87be0d84bccab1d773e3d3e0186):  I then updated the footprint in my pcb design and looked at the gerbers, and stilll see the solder mask:  Near as i can tell, all the pads necessary from the steps are there (exploded view): 

@bryan_6020, Getting nearer. Just to check, you have Solder Mask set to some minus value for the large square 'pad' (on the bottom layer) but do you have a similar minus value for the Solder Mask on all the round pads (53) too? These I assume are on the Top layer, thats how I did it anyway. _ Regards.

@bryan_6020, @mrtom528, In my example there are only a square top layer pad, a square bottom layer pad and 4 round multi layer pads. There are no separate round single layer pads. The negative extensions are applied to the bottom layer square pad and all the round multi layer pads. The top layer square pad has the normal, default extensions. Step 8 in: [https://easyeda.com/forum/topic/How-to-remove-the-exposed-copper-close-the-solder-maks-aperture-in-a-through-hole-pad-5673aa46a6a34172ae2ad9ade57aaa87](https://easyeda.com/forum/topic/How-to-remove-the-exposed-copper-close-the-solder-maks-aperture-in-a-through-hole-pad-5673aa46a6a34172ae2ad9ade57aaa87) places the Bottom Layer square pad.

@andyfierman, Yeah, that's what I did [eventually LOL] too....the only difference being that I removed an area of Solder Mask from the top, and yes, I know I said 'Top Layer' for the round pads but you know I meant 'Multi-Layer' (It was early when I wrote that) :) _ I can only assume that the OP hasn't set the Solder Mask on those round Multi-Layer pads, hence my asking them just to check. _ Regards.

ZOMG, i finally got it. I removed the extra bottom pads and had to set the solder mask on the multi-layer pads, as @Mrtom528 mentioned. what a relief. thanks for all the help.

@bryan_6020, Good to hear you finally got it sorted. Regards.