Sorry but as already pointed out, your project is private so only you can see it therefore it is difficult to offer meaningful advice. Please post a link to a public project that demonstrates this behaviour snd as advised earlier please study: [https://easyeda\.com/andyfierman/Welcome\_to\_EasyEDA\-31e1288f882e49e582699b8eb7fe9b1f](https://easyeda.com/andyfierman/Welcome_to_EasyEDA-31e1288f882e49e582699b8eb7fe9b1f) I suspect you are experiencing these problems because you are creating a PCB directly in the PCB Editor without creating a properly documented schematic first and then converting that to a PCB. We do not recommend creating a PCB directly in the PCB Editor with no schematic but if you really want to do it this way please see: [https://easyeda\.com/forum/topic/How\_does\_the\_Connect\_Pad\_to\_Pad\_tool\_work\_\-JgQO0Ay7H](https://easyeda.com/forum/topic/How_does_the_Connect_Pad_to_Pad_tool_work_-JgQO0Ay7H) You may also find this thread helpful: [https://easyeda.com/forum/topic/PCB-layout-DRC-error-when-ending-wire-4d7dc84744244b06919a51b5b29a5b3b](https://easyeda.com/forum/topic/PCB-layout-DRC-error-when-ending-wire-4d7dc84744244b06919a51b5b29a5b3b)

Hello @andyfierman , I started with a schematic generated with EasyEDA, using parts from the library.  The netlist was then converted to a PCB, giving me a rat's nest connectivity diagram.  I placed the parts to minimize crossovers. I'll try to come up with something I can make public.  This particular design may actually turn out to be worth something. Thanks, Mark