Can you post a link to an example project (or file but not just an image) where this is happening? Thanks.

Was working on a module. hard to get a link but try this https://easyeda.com/editor#id=d9aaba37b509458c817f457a0326d607

OK, I'm not sure what may be causing the issue you describe but I think there are one or two other issues that you need to address before you reach the point of being able to successfully submit and receive back a functional PCB. * Once those issues are addressed then it is possible that the misalignment issue may sort itself out and if not, it will be easier to see what the underlying cause may be. 1) First thing you need to do is to press the `K` key (Fit in Window) then go to the panel on the right hand side of the window and click on the tab at the top where it says **Design Manager**. Scroll down and click `Refresh` next to `Nets`. PA0 through PA3 have warnings crosses next to them. Clicking on each of PA0 through PA3 in turn will highlight the nets. You will see that there are unconnected pads and/or nets. PA3 in particular has a net way off outside the board outline: ![enter image description here][1] Scroll down to check the other nets with warnings: ![enter image description here][2] 2) Scroll down to `DRC Errors`. Click refresh. Click on to check and then correct all DRC errors: ![enter image description here][3] It looks like this layout is built without a schematic and is just a collection of carefully placed pads (and drawn-on outlines) which have then been wired up. The only thing I have found that actually has a package is the connector **P** `TERMINAL_BLOCK_2P_5` and that appears to have been placed over a pair of what look like manually placed pads. It is hard to tell if the pads or outlines have moved between you saving it last and me opening it so I'm not sure if the misaligned and overlapping traces: ![enter image description here][4] and oddly placed pads which although appearing to be connected are not properly (as they have not picked up the net name that passes by them) ![enter image description here][5] are due to this alignment you describe or not. * It may also help to have a look at: https://easyeda.com/forum/topic/The_best_way_to_design_a_PCB_in_EasyEDA-ThR3pwqIC https://easyeda.com/forum/topic/How_does_the_Connect_Pad_to_Pad_tool_work_-JgQO0Ay7H https://easyeda.com/forum/topic/Essential_checks_before_placing_a_PCB_order-UuohztL3l [1]: /editor/20161028/581286fb78332.png [2]: /editor/20161028/5812878ff18fd.png [3]: /editor/20161028/581288482f2ed.png [4]: /editor/20161028/581286379cc54.png [5]: /editor/20161028/581286aec1b1f.png

Thanks for the help. Yes, this is just a try EasyEDA out board design. No schematic underlies it. But the comments are helpful. While I've got you. Showing all the copper on the top level is fine. But is there anyway not to show it? It makes it difficult to see the bottom layer. Another board I'm working on has it all black and transparent.

Click on the empty PCB area. Right hand panel: find and click on copper area visibility. Set to invisible. (No screenshots as this is from my not-so-smartphone.)

Thanks Andy. Worked like a charm. Ken

I'm guessing that you already know that clicking on the little eye icon in the PCB layers list menu toggles the visibility of the whole if a layer. :)