I found [this post](https://easyeda.com/forum/topic/Overlapping_copper_areas_on_the_same_net_dont_fully_merge_-0ASM4mEVP) from 5 years ago, and did as [andyfierman suggested,](https://easyeda.com/andyfierman) making the overlap larger, placing a via inside and giving it the Net name of the CopperArea. This, unfortunately, did not resolve the error. There are two sets of CopperArea(s). The one depicted with two regions highlighted shows a Via inbetween. The other shown, but without the regions highlighted, has 3 CopperArea(s) with 2 Via(s) connected by a line, presumably because they have the same Net name. Strangely, the 3 CopperArea Via(s) do not have a line connecting them to the pins, where as the 2 CopperArea Via is connected to one of the pins. This is my first time using EasyEDA. I am a hobbyist who has only done a few boards in my life. I am planning to have JLCPCB build and assemble the boards. Thank you for any assistance.