You need to use EasyEDA editor to create some projects before publishing
PCB file to save via grid parameters
563 6
topirinkinen 3 years ago
Hi, Is it possible to get feature which saves via grid parameters (diameters & spacings) to CopperArea. So that when I open the PCB file later, I don't have to enter them manually (and try to remember what values I used). ![image.png](//image.easyeda.com/pullimage/nyaZEQ4vPyPFhbA5sI0mvILv4siSdr2DqL38jqNy.png) -Topi
Comments
andyfierman 3 years ago
Are you saying that you place them, save then close the PCB but when you reopen the PCB, the vias have been deleted? Are you sure that they are no just hidden so if you rebuild the copper area, then they reappear? If they really are deleted then please change the Category of this topic to **Bug** **Repor** .
Reply
topirinkinen 3 years ago
Hi, No, the vias are not deleted. What I am looking for, is the save of the parameters. If I edit the pcb, and need to re-create the via pattern. Now I need to remember what was the diameters&spacings. -Topi
Reply
andyfierman 3 years ago
@topirinkinen, "If I edit the pcb, and need to re-create the via pattern" For example if you want to create a new copper area with the same pattern of vias in it?
Reply
andyfierman 3 years ago
@topirinkinen, Can you not just copy and paste them? Or use the **Group/Ungroup** tool? ![image.png](//image.easyeda.com/pullimage/xuC8rK8sBLkc522e6wo3e3VCIEWJFyVbd6GFxcKY.png)
Reply
MikeDB 3 years ago
As well as saving the grid parameters, it would be nice if it saved the default standard via parameter for each user.   I always use 30/15 rather than the 24/12 EasyEDA offers as a default, but don't want to change the DRC rules as sometimes I do have to use 24/12 to avoid a DRC error.
Reply
topirinkinen 3 years ago
@andyfierman, Not copy paste. I mean e.g. following scenario: I have this PCB design done: ![image.png](//image.easyeda.com/pullimage/l49PonFCYpueIH7WB3SV8dRCYXg5ccDYozpywU31.png) In the middle you see a tighter via pattern (where C3 is located). I need to add one capacitor more next to C3. If I don't do anything to the via pattern, the via pattern interferes with the new wires and new pads (DRC violation). What I have done so far: I delete the via pattern: ![image.png](//image.easyeda.com/pullimage/CJMkw9jirYN29GhV4v1vl2ZoepNYJCNT3GzVfcLb.png) And then I create the via pattern again for the same CopperArea. In this CopperArea the via pattern was 0.8 mm spacing, but the default value in ![image.png](//image.easyeda.com/pullimage/RNy08iaOSj0kpnI4Y43JVFbhFkMIOXjZqwlOobM5.png) seems to be 5.080 mm. I need to remember what parameters I have used in this area earlier, and enter those values manually to this command. What I would like instead: The EasyEda saves the via pattern parameters into CopperArea object. And if I ask EasyEda to re-create via pattern, it offers the values used previous time. -Topi
Reply
Login or Register to add a comment
goToTop
你现在访问的是EasyEDA海外版,建议访问速度更快的国内版 https://lceda.cn(需要重新注册)
如果需要转移工程请在个人中心 - 工程 - 工程高级设置 - 下载工程,下载后在https://lceda.cn/editor 打开保存即可。
有问题联系QQ 3001956291 不再提醒
svg-battery svg-battery-wifi svg-books svg-more svg-paste svg-pencil svg-plant svg-ruler svg-share svg-user svg-logo-cn svg-double-arrow -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus- -mockplus-@1x -mockplus-

Cookie Notice

Our website uses essential cookies to help us ensure that it is working as expected, and uses optional analytics cookies to offer you a better browsing experience. To find out more, read our Cookie Notice