The whole of EasyEDA can be searched using the search box in the upper right of the forum pages. Then select the forum tab of the search results. Your questions about copper areas are all answered in this section of the Tutorial: [https://docs.easyeda.com/en/PCB/Copper-Pour/index.html](https://docs.easyeda.com/en/PCB/Copper-Pour/index.html)

@andyfierman Hi, Thanks. It seems that on the mobile version of the website the search function doesn't appear or at least I couldn't find it :). Anyways I know about the tutorial - I studied that part too. I know about copper fill options like keep islands or not, clearance, etc. I played with those and I noticed the effect by altering the settings. Still there are cases when some artifacts are left behind as seen in the picture that I put when I started this topic. And as a matter of fact it makes sense for the fill algorithm to "fill" as much as possible the PCB as it tries to connect all the ground points this way. Maybe it's hard to make it "guess" when not to leave those artifacts behind as it happened on my board and on some other boards that I designed using this great tool. By tweaking the copper fill settings I can get rid of those unwanted artifacts that's true but sometimes it gets annoying (I can live with that so no worries here :) ). I appreciate the hard work and effort that you put on creating this **free **tool so for me it's a great thing to have and I cannot ask more of it. I tried to help by testing it and post some possible bug(s) as other users do to improve this great tool in the future. Thanks again for your help and quick response.

@mtiutiu, Thanks for the good comments and your positive feedback. I had noticed but had not got around to it so I will post a bug report about the missing search box in the mobile version. As long as the remaining bits of connected copper are no less than the minimum trace width (as set in the Design Rules), there should not be an issue. If they are being created at less than the minimum trace width then there is an issue that needs to be addressed. One last thing. I must point out that it's not my software, I'm just part of the EasyEDA team. :)

OK. I can confirm that those traces left behind are much more thin than the drc setting and because of that I got unconnected ground points on my board. This is a serious problem because I always leave the ground plane filling to connect all my ground points from the board and rely on it to do the job. So because of those very thin traces that the fill algorithm leaves behind it shows me that there are no issues in the left panel where I check the board electrical connections but in reality it's not OK. In the manufacturing process those very thin traces won't be created so I get an unusable board. I will confirm this when I get the real boards... oh joy...

Coming back with some updates. The down below pictures should indicate better where the issue is: In the first picture I'm using a 20mils GND plane copper area clearance and it creates that very thin line on the edge of the board which connects the ground plane from the right part of the board with the one from the left part of the board - I highlighted that too. This is not right because the pcb manufacturer won't create that thin line so in the second picture where I increased the clearance factor to 22mils it can be seen that I get a ground plane disconnection - that rat line appears. And it clearly comes out when you compare both pictures that there's no other path for the ground plane to connect to the other side of the board. Please note that on the  bottom side of the board there's no connection either via other components or vias. So this is a bug in the copper fill mechanism because it connects my ground planes via that very very thin line and the DRC doesn't complain and I get a ground connection which is valid from the software point of view but in practice this is not valid. So my opinion here is that the fill algorithm shouldn't create those very thin lines at all and the DRC point that there's no connection. I hope that I made clear my point here. And yes in other softwares (like KiCAD for example which I'm using also) this doesn't happen and I can rely on the ground plane to create valid connections between different areas on the board where applicable - where not I get a rat line and I must take action to connect that part of the ground plane too. This is clearly a bug and it's a serious one IMHO so please correct me here if I'm wrong. Thanks.

@mtiutiu, Some questions: 1. What is your minimum trace width set toin the Design Rules? 2. Do these very thin copper lines appear in the Gerber files? 3. Can you post the same image as:  but showing the board outline?

@andyfierman Answering to your questions: 1. **10 mils** 2. **YES** 3\. Posting the image from the Linux **gerbv** output (here you can find the [gerber files](https://file.io/uNiJcN) that I sent for fabrication ):  And the board with the outline also (it overlaps over that thin line of copper that gets generated but it's there !!! ): 

And here's the [project](https://easyeda.com/editor#id=|5712bc35dc9a4e6cbfb1e0333495a4ec|116250718d484f46936b3ed00d84a5c2) \- I made it public \(nothing secret of fancy here :\) \)\.

DRC shows some complaints about those thin lines that's true but the message is misleading - **Track to Track**. Other than that the **Nets** panel shows that the electrical connections are ok - which is not right because that thin trace is not ok. I know that it doesn't know and it cannot guess but the ground fill shouldn't happen at the board edge in this manner so that's where the real problem is in my opinion.

Hmmmm, If you don't see any of these very thin strips of copper anywhere other than at the board edges then I suspect the problem is due to a bug in how the copper area fill interacts with the board outline. That might give the developers a lead to work on.

@andyfierman Yes that seems to be the issue and in some areas of the board I don't like how the fill happens - it's still to thin or doesn't respect DRC settings. Other than that on a previous project that I worked on I didn't noticed this kind of behavior -  the copper area fill was working much more better. I was using an older version of EasyEDA - I think two or three revisions earlier than the current one. And no, it wasn't because of the DRC settings or whatsoever.

Hi, @andyfierman I'm still seeing similar issues on my board with really thin fills at places (especially between traces). Is there a solution to this problem yet? Thanks

Hi The thin lines we will solve that at next two big versions. maybe v6.2 at present, please change the copper area clearance or DRC clearance first.

@UserSupport Any dates for next releases ?   I can't ship my current board until I fix this problem and it's hard to exclude the areas where it's happening from the ground planing software.

@MikeDB  Maybe 3 months later

@UserSupport 3 months? This forces me to stop using EasyEDA and redo everything in KiCAD or other software instead :-/

@dimman Same problem here.  What I've done is created a really complex outline to the ground plane excluding every area where one of those thin tracks was.  Only solution I could think of other than the hassle of changing PCB tool again.

@dimman @MikeDB we will try to acheive it in 2 months, it is in v6.1 plan

@dimman @MikeDB Hi The demo is working now. we will try to release it at v6.1, maybe in February.