Can you show your PCB where is the problem? Are you run a DRC test?

Hi Jleith, Your public copy of what seems to be this schematic: https://easyeda.com/editor#id=AnhztL3Xf has been edited since the screenshot that you have posted above. To be sure about the cause of the error, can you also share a copy of the *exact* schematic from which you generated the PCB? If you have edited the schematic since generating the PCB, you may be able to recover it using the `Version History`: ![enter image description here][1] or possibly: **Home > My Account > Recycle** For reference, there are some guidelines of things to check before submitting Gerbers for fab here: https://easyeda.com/forum/topic/Essential_checks_before_placing_a_PCB_order-UuohztL3l Thanks. [1]: /editor/20161007/57f75f61d4897.png

Hi Andy I found the step to make the Schematic Public The Master is Aug27 - Rev 2 John

Just as a sanity check... Is this the right project? https://easyeda.com/Jleith/Master_Pitch_Count-bd60iASM4 When I check the schematic: https://easyeda.com/editor#id=aXtnFXR9r and the PCB: https://easyeda.com/editor#id=7ujhkWlpF I can't find any (short circuit) connection between the VCC and GRD (ground) nets. The Design Manager for both Schematic and PCB show no errors (although there are a lot of unconnected pins in the schematic which could be cleared from the Design manager by attaching 'No Connect Flag' (`X`) symbols to them in the schematic). I have also regenerated the Gerbers from the PCB file and can see nothing that would cause a short circuit across the supplies. However, the PCB file in this project has some additional copper (which I suspect you meant to put in the Documentation layer) that I am assuming isn't on the PCB that you originally submitted to EasyEDA so I am not 100% sure that I am really looking at what you have actually been supplied with. So, a couple of questions: 1. Since you have more than one bare PCB and they are only two layers, have you checked them visually for any shorts? 2. Have you checked them electrically for a short circuit?

Hello Andy Yes the https://easyeda.com/Jleith/Master_Pitch_Count-bd60iASM4 is the correct drawing THe SHORT is caused by the PIC PIN 18 connect to +5 the cutting of the #2 traces removes the +5 from pin 18. The number 2 cutting is result of the PCB routing picking up the trace of the RED dot and joining the traces . The #3 is a total mystery. The #1 cut is a error on the routing to the correct pin. Here is a image of the new wiring in Green Once I made the cuts the PCB works as designed. ![Corrected wiring][1] [1]: /editor/20161009/57f961b2edf32.jpg

Hi John, OK I misunderstood which nodes the `dead short` is between. Looking at the schematic and your original screenshot, then sorry but pin 18 *is* connected to the +5V (VDD) net. This is simply because you have drawn the wire from pin 18 so that it crosses the join dot on the +5V net. * Any wire that joins another at a red join dot or crosses another at a join dot **will** be joined. So the PCB is correct to the schematic. The schematic is also correct as drawn. It may not be what you *intended* to draw but the connectivity is correct to what you have *actually* drawn. The reason you didn't spot the error is maybe because you missed one or more steps in the checking process using the Schematic Design Manager tab in the right hand panel. ![enter image description here][1] After clicking on the Design Manager tab and then scroll down through `Components`, if you **Refresh** `Nets`: ![enter image description here][2] and then click on net `U3_6`: ![enter image description here][3] you'll see that the whole of the net *including the section to/from U1 pin 18* lights up red. You'll also see that in the `Net pins` section that is filled in when you click on U3_6, the pin U1 18 appears in the list of pins connected by the selected net. #### Ways to help avoid this sort of mistake in future. Now there are a number of things that make it hard for you to spot net related errors when checking your design and they also make it pretty much impossible for any sort of design manager to warn against. 1. Never draw wires so that they overlap. It makes the schematic very hard to read and to check. It is also not good schematic drawing practice. EasyEDA has done a pretty good job of not arbitrarily joining all the wires that you have drawn in such a way that they go to different pins whilst having sections that exactly overlap but it would be very easy for EasyEDA to join them if those lines were moved or redrawn and you may never spot the join. If you want to tidy the wiring in a schematic then join wires just by netnames and/or use the `Bus` and `Bus entry` tools in the wiring palette. 2. Never draw more than 3 wires at a join. 3 wires at a T junction is obviously a join. 4 wires joining at a single point with all 4 wires at right angles could be a 4 wire join or it could be an accidentally joined crossing of two wires. It makes reading and checking a schematic hard and again is not good practice. If you need to joins 4 wires then split the junction into two staggered 3 wire T junctions. 3. Never end a wire at or cross a wire over a join dot: any wire ending at or passing through a join dot **will** be joined at that dot. 4. Don't extend wires beyond the ends of symbol pins. That adds a spurious join dot on the wire which is not just poor drawing practice, it distracts and confuses the eye when checking connectivity and so makes it harder to spot mistakes. 5. Manually assign unique names to all nets. This makes it easier to spot in the Design Manager if two wires with different netnames are accidentally (or intentionally!) joined when editing. If they are just automatically named by the schematic editor then if they are joined it is harder to spot in the Design Manager that the editor has automatically renamed the whole new net and removed one of the old netnames. When checking using the Design Manager, the whole of the selected net lights up red so it is easy to see if two nets that should not be are joined. Uniquely naming nets also generally makes reading and therefore checking the schematic easier. One caution however: care must be taken that netnames are indeed unique. Re-using an existing netname does **not** trigger any warnings. 6. Avoid using red wires as they no longer change colour when selected! These various points are illustrated in the screenshots below: ![enter image description here][4] ![enter image description here][5] BTW, the wire to/from pin 18 may not *look* as though it is joined by the red join dot because it appears to be on top of it. That is however simply an atrefact of the way EasyEDA drawn objects: an object drawn after another will appear to be on top of it. If you select the join dot and then click on the `Align` button: ![enter image description here][6] and then click on `Bring to Front` then the join dot will appear on the top of all the wires. Similarly, selecting the wire to pin 18 and then clicking on `Send to Back` then that too will make the join dot appear on top. [1]: /editor/20161009/57f9776a9e989.png [2]: /editor/20161009/57f97231bc788.png [3]: /editor/20161009/57f9728bd128d.png [4]: /editor/20161009/57f96bfae843d.png [5]: /editor/20161009/57f96c83928fb.png [6]: /editor/20161009/57f9791a2b03e.png

Hello Andy I do follow your review of the endless mistakes I have produced. I was having a terrible time repostioning the part so I could have room to do direct wiring. I was sure there was a way to move the part and the wiring would be "Glued" and follow the new location. I tried and several different ways and nothing worked. I was using the wider "Green" to make it easier to ensure the correct parts. Aslo the +5 "Blue" it was not alwasy possible to ensure the GRD wire were correct. I have done about 10 projects and almost everyone I have messed up. With flipping connectors. I did have a lot of commponents to connect. I didn't know the "Design Manager" could point out errors. I only had it stop me from generating a PCB if I named the pins wrong or the device name. John