@[UserSupport](https://easyeda.com/UserSupport) @JLCPCBsupport chime in on this?

"I have created simple rectangular PCB as I have done many times before, using the latest client version of EasyEDA." Is this a single large outline within which you have then drawn 3 V-Cut lines to create the panelisation? "I have panelised the board, 1 column by 4 rows, no row spacing, no border. Within EASYEDA it all looks exactly like you would expect." For clarity, could you describe step by step exactly that you went through to do this. BTW; your image shows 1 column by 5 rows.

@andyfierman * I drew a single, contiguous, rectangular board outline first. * I then placed all the components, did the auto-routing tracks etc, adjusting the outline as needed. * Then I used the Tools > Panelise to panelise the board into 5 (yes, not four) rows, 1 column. No manual V-Cuts drawn. Initially, I did not spot that EasyEDA had a default 2mm gap between rows so I changed it to a 0mm gap when I re-panelised the board. At all stages, in EasyEDA, the board outline looked OK. This _might_ have caused the issue but even after deletion of the board outline the problem persisted (see below). After JLCPCB rejected the PCB submission, I deleted the outline, repeated what I have written above and resubmitted, which also got rejected with the _same_ issue. No matter how I generated the panelisation on this board the same, corrupted outline issue would reappear (only visible using the Gerber viewer). Generating just a single PCB (no panelisation) was fine, according to Gerbv. Eventually I created a brand new PCB with its default outline, changed it to the correct size, pasted in all my components and tracks, panelised it as described above and it was fine, according to Gerbv. It's (still) being made now. One of the problems here is that EasyEDA does not show what the Gerber File viewer shows (in relation to the board's outline) otherwise I would have spotted it immediately (and, yes, I know JLCPCB state that we should always check our Gerber File submissions 😉 using Gerbv but I never had to up until now, as it's yet another, slow step, although not as slow as having your PCB submission rejected four times 😯).