Hello,
In some case, when you penalize your board,positioning holes and fiducial mark are placed on a v-cut route.
JLCPCB don't like that :)
![panelize.png](//image.easyeda.com/pullimage/la53cDlFcenHn1Ss3fykW7DAIc29jH7ocvMWMwsT.png)
Have nice day,
Thank to the team for this really good tools
Firefox
85.0
Windows
7
EasyEDA
6.4.16