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Panelize : Bad placement of positioning holes and fiducial mark they are on on v-cut
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rom1nux 3 years ago
Hello, In some case, when you penalize your board,positioning holes and fiducial mark are placed on a v-cut route. JLCPCB don't like that :) ![panelize.png](//image.easyeda.com/pullimage/la53cDlFcenHn1Ss3fykW7DAIc29jH7ocvMWMwsT.png) Have nice day, Thank to the team for this really good tools
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你现在访问的是EasyEDA海外版,建议访问速度更快的国内版 https://lceda.cn(需要重新注册)
如果需要转移工程请在个人中心 - 工程 - 工程高级设置 - 下载工程,下载后在https://lceda.cn/editor 打开保存即可。
有问题联系QQ 3001956291 不再提醒
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