Obviously Top Silk layer over bare copper Upper layer and same for Bottom silk. Possibly adapt a copy the DRC code to rather than starting from scratch ?
Do you want:
1. A warning for any silkscreen overlapping exposed copper;
2. Any silkscreen overlapping exposed copper to be removed (as JLCPCB will do anyway during PCB fab)?
Our website uses essential cookies to help us ensure that it is working as expected, and uses optional analytics cookies to offer you a better browsing experience. To find out more, read our Cookie Notice
Brand new interactions and interfaces. 
Easy to use and quick to get started. 