Is this the link you are trying to post? [https://easyeda\.com/Jaan\_Doh/p8x32a\_shield\_v01](https://easyeda.com/Jaan_Doh/p8x32a_shield_v01)

Well done: you have placed decoupling capacitors in most places where they are needed. Many people omit them. Most of your 1uF decoupling caps could safely be reduced to 100nF. However, the schematic is not well laid out. It is hard to read and harder to spot errors. Please study: [https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a](https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a)<br> <br> and the documents that it links to, especially (2.2), (4) and (6). They will save you a great deal of time and stress. When you have a well constructed schematic that converts to PCB without errors or warnings, then you will learn more about good PCB practice routing it by hand than simply running the Autorouter and watching it mess everything up. You can use an autorouter but you need a lot of experience with hand routing first in order to understand what matters in a PCB layout and what you can afford to let the autorouter run away with because it doesn't matter how it routes those parts. :)

@andyfierman, Yes that' s the link/page, thank you...

@andyfierman, Oh dear, it looks like the many iterations of the design process has got me confused,  I had thought that I had used 0.1uF capacitors for decoupling. I guess through copy and pasting things got mixed up, nice one for pointing that out to me.... I will run through the components and make the changes as required and replace the 1uF capacitors with 0.1 uF ones instead. I ended up using the auto router because I had several DRC errors related to pad and track spacing which I was unable to resolve, I spent hours looking at the error information and shuffling tracks around but was unable to understand why the issues were flagged as errors because for example I had a hole/pad on the pcb where a component was placed and then I had 2 or 3 tracks going to the hole/pad and I could not understand if it was because there were separate tracks or something else completely as the spacing looked way more than the minimum limit for spacing... It would be super if the examples in the tutorial covered more than just showing 2 pads overlapping which is quite obvious and evident that something is incorrect... When I was unable to resolve the DRC errors, that made me think that something must be electronically wrong with my design, and having seen other projects go up in that famous blue smoke and smell of silicon burning, I wanted to be sure that I do not order PCB's which are badly designed and useless because of it. So I posted my question here. Some of the bits still confuse me like faint blue rat lines remaining on the PCB design, even though the track is routed to account for the rat lines... I did do brief searches to see if other members had the same issue and how they resolved it, but couldn't find a solution. Anyway, thank you for the help (especially in pointing out the 1uF caps where they should be 0.1uF) I'll be sure to read the docs you linked to, especially the "Essential checks before clicking the Convert Project to PCB" once I have corrected the errors in the schematic, and the one about Finally, where you stated above... "**_However, the schematic is not well laid out. It is hard to read and harder to spot errors._** **_Please study:_** [**_https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a_**](https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a) **_and the documents that it links to, especially (2.2), (4) and (6)._**" I found the 2.2 link which I guess is the link to the How to ask for help and get an answer document/page... but after 2(2)the numbering stops and I was unable to find (4) and (6) links. <br> <br>

You have to follow the linked documents. (2.2), (4) and (6) are linkes from (2) which is a link from the how to ask page.

If you have ratlines left then you have bits of copper which have the same net name but which are not physically connected to each other. That's really all there is to it: you just have to see why that is and fix it. A common one is that people put a copper area in and assume that will connect everything on that net. In fact it may not as you can have a copper area form around a pad with a net name but which copper from around it cannot reach so you have an isolated, incomplete net. Hence a ratline.

@andyfierman Cheers for that, I'll have a look at the linked documents from the first linked document. With regards to the copper fill/area, where unconnected islands can occur because of surrounding copper areas, I only learned how to use the copper fill yesterday, but maybe there were copper track bits left further below, so i'll watch out for that in the future. Thanks again.