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Problems with VCC vs +5V netflags in simulations.
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andyfierman 3 years ago
In answering this topic: [https://easyeda.com/forum/topic/voltage-source-simulation-pcb-implementation-dabdd889176c4cb2a7de722c3031bb9e](https://easyeda.com/forum/topic/voltage-source-simulation-pcb-implementation-dabdd889176c4cb2a7de722c3031bb9e) it has been found that there are problems with the internal voltage sources that EasyEDA auto-assigns to simulations when netflags such as VCC, +5V are assigned to nets. * This causes this simulation to be produce rubbish results which was not noticed by the user as they are a self-confessed novice. It looks like as long as any other explicitly placed voltage source in the sim **does not share** a common net (other than ground or 0) with an EasyEDA auto-assigned voltage source **then all the voltage sources are netlisted correctly**. However, if any other explicitly placed voltage source in the sim **does share** a common net (other than ground or 0) with an EasyEDA auto-assigned voltage source **then some or all the voltage sources are not netlisted correctly**. Sheets Sheet\_1 to Sheet\_4 and Sheet\_6 and Sheet\_7 in this project: [https://oshwlab.com/andyfierman/vcc-vs-5v-netflag-problem](https://oshwlab.com/andyfierman/vcc-vs-5v-netflag-problem) demonstrate this issue by pasting the netlists into the schematics as text. * **Until this issue has been resolved it is recommended that all required voltage sources MUST be placed explicitly in the schematic as shown in Sheet_5 to correctly netlist all voltage sources.** Voltage sources can then be connected to other nodes using netflags without the netflags invoking additional EasyEDA auto-assigned voltage sources.
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dillon 3 years ago
If the user has a voltage-source, we don't auto connect . If without , we will add it.  so it seems no problem for this .
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andyfierman 3 years ago
@dillon, My examples that show the problem are based on how V1 and V2 are connected in this user's schematic: ![Screenshot_20210226-101342_Chrome.jpg](//image.easyeda.com/pullimage/6zA4ccbBmttHGRXPN2YQtrx1oWHvepE3tP0y5LGZ.jpeg) So there is a problem because although this may be an unusual way to connect voltage sources: 1. It is a perfectly valid way to do things;  2. It is a real user example;  3. The user gets no warning about what EasyEDA has done and how the changes that EasyEDA has made, makes the simulation netlist different from what the simulation schematic shows them; 4. Based on their simulation results, this user was about to create and order some PCBs for a project that - because of the auto-assigned sources - would not have worked correctly. In other words, the simulation that the user is running is not what the schematic shows them because EasyEDA has changed the arrangement of the auto-assigned voltage sources without warning them. The rules for auto-assigning voltage sources need to be changed to either: 1. allow for any configuration of voltage sources in a schematic type of connection or;  2. Warn the user that they must add explicit voltage sources for all supply rails to avoid a possible conflict with auto-assigned sources. I fully understand why auto-assigning voltage sources is so attractive for users, especially novices but if this feature is to be included in EasyEDA, it must be absolutely user-proof. :)
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andyfierman 3 years ago
@dillon, Sorry but I have just found another example of where the EasyEDA auto-assigned voltage sources break a perfectly valid simulation (and in fact one that has worked OK since It was created around 2014): test jig 01 tran, test jig 01 tran, MCP6041EE test jig 01 tran, generic opamp test jig 140227 and LM108 opamp test jig 140312 in: [https://easyeda\.com/andyfierman/The\_EasyEDA\_5\_pin\_parameterised\_opamp\_model\-7HBTNtKEW](https://easyeda.com/andyfierman/The_EasyEDA_5_pin_parameterised_opamp_model-7HBTNtKEW)<br> <br> have some 0V voltage sources embedded in the Ammeters in series with the supply rail voltage sources and also have the commonly used netlabels VCC and VEE assigned to indicate the positive and negative supply rails. For reasons that I do not understand however, test jig 01 tran, test jig 02 tran fail because the voltage source auto-assignment process misunderstands how the explicit supplies and the voltage sources in the Ammeters have been connected up. MCP6041EE test jig 01 tran, generic opamp test jig 140227 and LM108 opamp test jig 140312 run OK despite the fact that, apart from a difference in the .tran time and the parameters used in VSIG1, _generic opamp test jig 140227 and test jig 01 tran are the same simulation schematic!_
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dillon 3 years ago
@andyfierman It is hard for this.  Too many users don't add power supply , and break the simulation.   I don't know how to choose, remove it easy In your case , you can change the netlabe VCC as VCC1 , vee as VEE1 ![image.png](//image.easyeda.com/pullimage/PxX9mW0lbtKhlhNifLqaFxzyUEeicriUWqvtOfh7.png)
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andyfierman 3 years ago
Maybe we are trying too hard to look after our users? :) In the Simulation Tutorial there is a section on "Avoiding Common Mistakes" which includes "Every simulation must have a power supply" and "Every simulation must have a ground". Each has examples to demonstrate the statements. We detect and warn when a user runs a simulation without a ground node. Can we do the same for a voltage or current source? What if we simply check the simulation and if it has as no voltage or current source and we ignore any that are inside a subckt (including the Ammeter) then we warn the user that they need to add a DC Voltage source to power their simulation circuit and that they may need to add a signal source too? We should not try be too clever. For example a check only for sources with one end connected to ground will fail where a sine voltage source is connected to the primary of a mains transformer and the secondary is connected to a bridge rectifier because the sine source may be floating whilst the negative side of the bridge is connected to ground.
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