"...is there a single time when copper areas shouldn't be rebuilt just ahead of fabrication?" Although not relevant in current versions of EasyEDA, I can think of one reason: If you have had to do some temporary net renaming to get a copper area to flood an area but clear a couple of tracks which - without the temporary rename - would be on the same net and so would also be flooded. If you temporarily rename the nets then do the copper rebuild, the nets - which may be for something like a Kelvin connection - will be cleared. Then you name the nets back to that of the copper area but do not rebuild the copper before generating the Gerbers. I did this to generate Kelvin connections to a 10mR current sense resistor on my Uberclamp project but that was on an eanrly version of EasyEDA before the options to copy and convert traces into No Solid regions etc., were implemented. **It therefore should be noted that there are now much better ways in EasyEDA to achieve what my example above set out to do, as illustrated in this topic: ** [https://easyeda.com/forum/topic/How-to-create-a-four-wire-sensing-or-Kelvin-Connection-on-a-PCB-8034986947764c1fb1a872de020160e8](https://easyeda.com/forum/topic/How-to-create-a-four-wire-sensing-or-Kelvin-Connection-on-a-PCB-8034986947764c1fb1a872de020160e8)

This also demonstrates why it is so important to go through the Essential checklist (6) in (2) in: [https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a](https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a) :)

@andyfierman, while it remains to be seen whether the boards were generated properly by JLC, the issue appears to be something different from what I said: the gerbers for my order of 5-6 boards show no tracks on any of the layers except for Top. So it's not what I first assumed (re-generating pours). That being said, my initial suggestion still stands: 99.9% of cases will benefit from re-generating the pours before gerbers are produced. Hell, it may even do so already!

Just checked. Pours don't automatically generate when creating gerbers. Imho, they should.

\>This also demonstrates why it is so important to go through the Essential checklist \(6\) in \(2\) in: [https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a](https://easyeda.com/forum/topic/How-to-ask-for-help-and-get-an-answer-71b17a40d15442349eaecbfae083e46a) @andyfierman I agree. My point is that I might have made a mistake (or not, since I usually hit SHIFT-B all the time) but the software should make it a bit harder for such mistakes to be made.

@martin, Yes, I agree with your points. IIRC, over a few earlier versions, Copper Pours were automatically rebuilt but I lost track of when that stopped. Now the copper is rebuilt each time a PCB is reopened. If that's not actually what went wrong in your case anyway then if there's anything I can do to help with the detective work, just post back.

Hey Andy, I'll take you up on that. I've shared a couple gerbers (on their way back from JLC now) here: [https://gofile.io/d/9PMN74](https://gofile.io/d/9PMN74) Gerber\_PCB\_2020\-08\-11\_12\-59\-03\_2020\-09\-30\_07\-04\-08\.zip does not show tracks on the back with the JLC gerber viewer \(scary\!\)\, but this viewer does: [https://www.gerblook.org/](https://www.gerblook.org/). Hopefully, fabrication will match the latter viewer. Project (please forgive the silly url): [https://easyeda\.com/martin/cc1352\-breakout\-to\-raspberry\-pi\-1b\_copy\_copy\_copy\_copy\_copy](https://easyeda.com/martin/cc1352-breakout-to-raspberry-pi-1b_copy_copy_copy_copy_copy) Gerber\_IPC\_layout\_update\_2020\-09\-30\_07\-07\-05\.zip does not show inner layer tracks and solid regions on any viewer \(scary\!\)\. This is a new version of a board that was produced successfully in the past\. Project: [https://easyeda.com/martin/cc1352-breakout_copy](https://easyeda.com/martin/cc1352-breakout_copy) Other boards from my order exhibit similar problems, but this is enough to see, I think. They'll be here next Tuesday so I can validate.

One question: can you remember when you switched over to Edge Chromium? And what from? Firefox?

From Chrome to Edge. Should be pretty much the same, wouldn't you say? Probably some time in August.

Setting -> System Settings -> Rebuild Plane Automatically. From my testing i'm not sure what triggers it to rebuild though. It may also only work with plane layers (like an inner plane)

Thanks @cjohnson, good to know. BUT, doesn't get triggered on gerber generation, just tried.

Hey, the DRC (design rule checker) detects short circuits as clearance problems, and it definitely asks whether you want to run DRC when you're exporting a new gerber file. Did you decline?

@leif, yeah, to be honest, I always decline because I also run DRC manually. That is a good point, though. In any event, the issue looks like a display problem with the way gerbers are generated by EasyEDA. Hopefully, it doesn't actually affect production.

You can always cound on FedEx to overdeliver. Boards have arrived ahead of time, and they are good. So this is either a display issue with the JLC gerber viewer, or a gerber generation issue with EasyEDA which affects the display, or a combination. Production is good.

I usually use he FOSS gerbv package to check Gerbers. The old EasyEDA never got there and the JLCPCB versions of Gerber viewers is not good enough to rely on yet.