Hi,
I have here a very simple example with the following: ([https://oshwlab.com/project/publish/77e48a82dcc04184b93db18f7a3ae015#](https://oshwlab.com/project/publish/77e48a82dcc04184b93db18f7a3ae015#)):
1\. 4 layer board with L1=GND and L2=V3\.3 \(as planes with the expectation that it will start off as all copper\)
2\. A battery \(with V3\.3 and GND\) and resistor \(connected to V3\.3 and GND\)
3\. The battery and resistor connected to vias with appropriate net names
Expectation:
All ratlines should disappear
Actual:
Only the GND ratlines are gone.  The V3.3 ones still remain.
What am I doing wrong?
Thank you
            
                        
            
                                    
              
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