For many chips with an exposed pad, the IC manufacturer recommends to put vias on the exposed pad for best thermal performance. However, there is some concern about solder paste voiding (e.g solder is wicked into the via during reflow). Some possible solutions to this problem are to "tent" the via with solder mask, or to plug / fill the via during manufacturing.
What approach does EasyEDA suggest for users of their PCB service?