Noticed some of recent PCBs have come back from manufacturing with exposed copper on some vias. Looking at EasyEDA Pro, these vias have a setting for the solder mask expansion set to 'custom' 0 for both top and bottom. I have not set this. If I select 'general', then back to 'custom', the fields then read -25.4 for both top and bottom, and the solder mask circle is removed.
This a bug?
I'd have thought by default vias should not have solder mask.
Holes are open top and bottom so no problems there.
Fair point, if you put a solder mask covering as an object using the solder mark layer, you are exposing the copper.
My point is still valid however above, vias put down by EasyEDA Pro (I think since the update) have exposed copper top and bottom by default - which is not how it should be - hence why I think it is a bug re the solder expansion settings. Ideas?
if you set it as general, you need to set the Design Rule of the solder mask expansion
Brand new interactions and interfaces. 
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By default vias should normally be covered by solder mask, i.e. there should be no exposed copper.
Note that this is not the same thing as "tenting" vias: by default vias from JLCPCB should have open holes on both top and bottom sides of the via.