All of the sudden there is a notice for rat tails on my ground Net, but I cannot find any in the PCB... Back to it.....

Never mind, as suddenly as the error appeared, it disappeared... Closed and reopened the file and all is well... Was about to pull hair out.

Can you post links to the relevant datasheets please?

My apologies sir. Please see the links to datasheets below. I will edit them into the body of my post as well.

Buck
https://www.st.com/content/ccc/resource/technical/document/datasheet/32/ba/a3/74/93/3f/4d/24/DM00064431.pdf/files/DM00064431.pdf/jcr:content/translations/en.DM00064431.pdf
10uF Cap
https://search.murata.co.jp/Ceramy/image/img/A01X/G101/ENG/GRM319R61E106KA12-01.pdf
Inductor
https://www.we-online.com/katalog/datasheet/744314330.pdf
R 20kohm
https://www.yageo.com/upload/media/product/productsearch/datasheet/rchip/PYu-RC_Group_51_RoHS_L_12.pdf
R 250kohm
https://www.yageo.com/upload/media/product/productsearch/datasheet/rchip/PYu-RC_Group_51_RoHS_L_12.pdf
1uF Cap
https://www.yageo.com/upload/media/product/productsearch/datasheet/mlcc/UPY-GPHC_X7R_6.3V-to-250V_22.pdf
22uF Cap
https://search.murata.co.jp/Ceramy/image/img/A01X/G101/ENG/GRM32ER61C226KE20-01.pdf
Cree LED
https://assets.cree-led.com/a/ds/x/XLamp-XPL.pdf

Also, here is the Gerb... Nice picture but I am not entirely sold on the fact that all the holes are truly through-drilled....

I found few mistakes from your project:

1. According to the datasheet of ST1S41PHR, EN pin needs to be pulled high to enable the device, not pulled to ground.
2. You only have one output capacitor. Usually there is primary and secondary capacitor at the output. You have two capacitors at the input, this is ok.
3. Exposed pad of the chip should be connected to GND.
4. Use only one GND symbol when using GND symbol at your schematic.
5. Your clearance distance is quite low / tight. Inrease this value to at least 0.2mm or to 0.254mm
6. You could also add GND via stiching near PCB outline

Regards,

Markus Virtanen
HW / Electronics Designer