Reversed pins on `RAD` series electrolytic cap footprints
805 1
andyfierman 3 years ago
**BUG** #### Concise problem statement: There is a problem with the `RAD` series of electrolytic capacitor package footprints. Their pin numbering is reversed so that the `+` pin on the symbol is mapped to the `-` pin on the footprint. * Other RAD footprints show same fault: https://easyeda.com/forum/topic/Electrolitic_capacitor_schematic_vs_PCB-Cc5nFlf9r #### Solution: The package pins on the `RAD` series of electrolytic capacitor package footprints need to be swapped. #### Steps to reproduce bug: 1. Place electrolytic cap and a resistor from EasyEDA Libs into a schematic; 2. Connect resistor to cap, one wire to each end; 3. Apply net labels, `POS` and `NEG` to wires to indicate cap polarity 3. Assign a `RAD-248` package to the cap symbol; ![enter image description here][1] 4. Pass schematic into PCB; Results: Netlabel `NEG` connects to `+` package pin and `POS` connects to other package pin ![enter image description here][2] Expected results: Netlabel `POS` connects to `+` package pin and `NEG` connects to other package pin. Browser: Chrome [1]: /editor/20161027/5811b39bd40ee.png [2]: /editor/20161027/5811b45c59bf6.png
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EasyEDA 2 years ago
The following **System** packages: RAD-197 RAD-248 RAD-315 RAD-394 RAD-492 RAD-630 RAD-709 have now been corrected. Copies of these parts from **any** other areas of the library are user contributed parts which can only be accessed by their contributors. These packages must be checked by the user prior to PCB submission. Please note that the following packages: RAD-01 RAD-02 RAD-03 are user contributed parts which can only be accessed by their contributors. These packages must be checked by the user prior to PCB submission. Please note that all packages and pin assignments should be checked by the user prior to PCB submission as stated at the foot of: https://easyeda.com/order ![enter image description here][1] For more information on essential pre-Project-Conversion-to-PCB and pre-PCB-submission checks please see (4), (5) and (6) in: https://easyeda.com/andyfierman/Welcome_to_EasyEDA-31e1288f882e49e582699b8eb7fe9b1f [1]: /editor/20180107/5a51670321264.png
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