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SVG Parse Error on PCB creation
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Guest 8 years ago
**BUG** Refer to project (public): https://easyeda.com/editor#id=moicuoGYR|0qysYSasJ Concise problem statement: Schematic passes Design Manager checks. Proceed to create PCB - Get "SVG Parse Error". PCB created with components but two components are missing: U2 and P2 Update PCB with "Import Changes" and get report. Missing components are identified but still generating SVG Parse Error (and not imported). Checked component naming convention as per (Bug Report: I get a message containing: "ERROR: SVG parseerror"), no success. **Check naming convention on nets - Renamed suspect names (possible illegal characters) - Success.** Regards AlanC Import Changes report: Add Component P2 Add Component U2 Change net U6_2: U10.2 U11.1 U13.1 U13.2 U14.2 U15.1 U16.1 U17.1 U17.2 U18.2 U19.1 U2.2 U2.4 U5.1 U6.2 U7.1 U7.2 U9.1 U9.2 Change net A2: P5.3 U13.3 U14.3 U15.3 U16.3 U2.5 U4.3 U5.3 U6.3 U7.3 Change net U2_12: U2.12 U6.11 U7.6 Change net GND: C1.1 C10.2 C11.2 C12.2 C13.1 C14.1 C15.1 C16.1 C17.1 C18.1 C19.1 C2.2 C20.1 C3.2 C4.1 C5.1 C6.1 C7.1 C8.1 C9.2 P6.12 U1.8 U10.7 U11.7 U12.7 U13.7 U14.7 U15.7 U16.7 U17.7 U18.7 U19.7 U2.7 U20.7 U3.7 U4.7 U5.7 U6.7 U7.7 U8.7 U9.7 Change net VCC: C1.2 C10.1 C11.1 C12.1 C13.2 C14.2 C15.2 C16.2 C17.2 C18.2 C19.2 C2.1 C20.2 C3.1 C4.2 C5.2 C6.2 C7.2 C8.2 C9.1 P1.1 U1.16 U10.11 U10.12 U10.14 U10.6 U11.11 U11.12 U11.14 U11.6 U12.11 U12.12 U12.14 U12.6 U13.11 U13.12 U13.14 U13.6 U14.11 U14.12 U14.14 U14.6 U15.11 U15.12 U15.14 U15.6 U16.11 U16.12 U16.14 U16.6 U17.11 U17.12 U17.14 U17.6 U18.11 U18.12 U18.14 U18.6 U19.11 U19.12 U19.14 U19.6 U2.14 U20.11 U20.12 U20.14 U20.6 U3.11 U3.13 U3.14 U3.9 U4.11 U4.12 U4.14 U4.6 U5.11 U5.12 U5.14 U6.12 U6.14 U7.11 U7.12 U7.14 U8.14 U8.3 U9.11 U9.12 U9.14 U9.6 Change net !LOAD: P2.1 U8.8 Add net CARRY: P2.2 U2.9 Add net P>Q: P2.3 U2.13 Add net P<Q: P2.4 U2.11 Change net !WRD: P2.5 U17.8 Change net !WRA: P2.6 U18.8 Change net !WRQ: P2.7 U19.8 Change net !WRP: P2.8 U20.8 Change net !RDPC?: P2.9 U9.8 Change net !RDSHR: P2.10 U10.8 Change net A1: P5.4 U11.2 U12.2 U15.2 U16.2 U19.2 U2.3 U20.2 U4.2 U5.2 Change net A0: P5.5 U10.1 U12.1 U14.1 U18.1 U2.1 U20.1 U4.1 U6.1 Change net U2_8: U2.8 U5.6 Change net U17_3: U10.3 U11.3 U12.3 U17.3 U18.3 U19.3 U2.6 U20.3 U9.3 Change net U2_10: U2.10 U6.6
Comments
dillon 8 years ago
Just fork your project and test. It is OK. Hope you can remeber which illegal characters , we should filter them.
Reply
Guest 8 years ago
Hi Dillon, Yes I fixed it before finishing the post but I thought it was worth while to post anyway (after you chastised me last time for not posting bugs!). I had: "PC?" (without the quotes) "P>Q" "P<Q" I suspect it was ">" and "<" but I did all three at the same time. Yes a good idea not to allow the invalid characters being used in the schematic. I this case I worked out what was going wrong. I also note that in-bedded spaces are removed in net names (i.e. "!RD P" -> "!RDP"). This could be a problem when "!RD P" and "!RDP" exist as separate nets in the schematic. I replaced my spaces with an "_" to avoid this. Regards AlanC
Reply
dillon 8 years ago
> I suspect it was ">" and "<" but I did all three at the same time. I think this is the reason, will dig this more. Thanks.
Reply
andyfierman 8 years ago
@AlanC, It is generally a good idea to not use spaces in any names in EasyEDA. As you have already tried, using the underscore `_` is the safe alternative to spaces. The hyphen character `-` is also not always reliable: it can cause problems in spice model and subcircuit names in EasyEDA and it may be replaced by code substitutions in file names.
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