@bryan_6020, Hello again Bryan! I can't be a great deal of help with the differential pair routing tool since I have not used it,  however... "...as I understand it, the Ethernet pairs between the PHY and magnetics need to be impedance controlled to 100ohm and they need to be routed (ideally) in parallel, and the trace space and trace width are important variables in the impedance control." In an ideal world that is correct but in practice as long as both traces are routed to the same length to within a couple of mm with an individual trace impedance of 50R and not crossing any plane breaks or slots then over a reasonable sized PCB (say a Eurocard of 160mm * 100mm) then they do not need to be routed as a closely coupled differential pair. Skimming over a lot of background from Dr Howard Johnson's books, High Speed Digital Design and High Speed Signal Propagation, this is because the distances between the traces can be made small enough that they would require interfering signals of several GHz before a half wavelength would fit - and so be able to generate a significant votage difference -between them. The same thing applies to radiated emissions from between the traces themselves. This is useful to know because the design and the repeatable fabrication of properly impedance matched differential pairs is quite tricky. The trace widths and the gap between them has to be carefully specified and controlled in manufacture because for them to behave as closely coupled differential pairs (i.e. most of the return path current is confined to the space between the traces on the ground plane), the gap has to be of the order of the trace width and as the gap reduces so does the differential impedance between the traces so the traces themselves have to be narrower than that of a single ended 50R trace would be to maintain the differential 100R impedance. There are calculators to work out trace width and separation for closely coupled differential pairs but you need to have a pretty well specified substrate (dielectric constant and layer dimensions) for tit to come out right on the board so really unless you are working with multi-Gigabit Ethernet or have no choice but to cross plane breaks, designiong for separate but reasonably length matched single ended traces should be good enough. Obviously try to avoid layer swapping (vias add discontinuities and so spoil the impedance control) and swapping from ground plane to power plane reference planes if on a multi-layer board. Swapping from on-top-of, to underneath a ground plane layer is not too bad as long as the trace widths are corrected for the difference between coated surface microstrip and internal stripline but minimising the discontinuities created by swapping reference planes gets very messy and without back annotation (EasyEDA only does forward annotation: schematic to PCB) is hard to manage properly. If layer swaps cannot be avoided then try to keep the layer swaps matched between the two traces and don't forget that the trace widths (and therefore gaps in a closely coupled differential pair) change between external and internal

Hey Andy! ok, that's interesting information. :) but i've already used the JLCPCB imedpance calculator for their stack ups and have calculated the necessary trace widths and spacing. I just am not sure how to make that work in EasyEDA. :) Thus far, I've just manually edited the tracewidth after routing, and eyeballed the spacing: 

Hi You can set the design rule for the differential pair nets first

Yeah, I thought I read that, but I couldn't find any documentation on it, and I don't see anything in the design rule settings for diff pairs. Can you tell me how to set a diff pair net rule, please?

[https://docs.easyeda.com/en/PCB/Route/index.html#Differential-Pair-Routing](https://docs.easyeda.com/en/PCB/Route/index.html#Differential-Pair-Routing)

Yes. That's exactly what I read. The extent of the doc is: "and you need to set Differential Pair net rule at the “Top Menu - Tool - Design Rule” first." Ok! But uh, that doesn't actually tell me anything about how to do it. :)

@bryan_6020 Just had a little play with the tool. * For differential traces, the **Clearance** attribute defines the inner-edge-to-inner-edge separation of the traces. * It also however, defines the outer-edge clearance to any other copper: which is not helpful when creating diff pairs since everything else has to be several times the inner-edge-to-inner-edge gap away from the outer edge of the pair (rule of thumb is probably more than 3x). If other copper is closer then it reduces the characteristic impedance of the trace in that area of encroachment. For the odd bit of copper, that might be OK but for a ground flood the effect would be disastrous. So care must be taken in setting clearances for other traces and copper areas to diff pairs.

ahhh, i see. i was looking for something specific diff pairs. i was trying to complicate the rules dialogue, i guess. thanks, Andy. Hope you're staying well over there.

This feature doesn't actually seem to work very well. I set my design rules for the various diff pairs:  And then ran my tracks, but the joint corners fail the DRC check: 

@UserSupport, I believe this is a bug. For now I'm just ignoring the error.

@bryan_6020, It could be that this is another manifestation of rounding errors. Have a look at the warning messages at the bottom left of the Design Manager panel and compare the clearance setting value for the diff trace design rule in both mm and mils units.