when the wire have serveral net labels, it is hard to be indicated which net name it is. We will try to improve this, thanks.

PLease note: As a rule all the netlabels on net drawn as a wire must have the same name even if the wire braches off to different places. Obviously, nets joined by netlabels must have the same name otherwise they will not be joined. In simulations, on nets that have netlabels attached to them, then any VolProbe placed on that net should have the same name as the net. This is because the name on a VolProbe overwrites the name set by the netlabel. If the names are different then this will cause problems with any behavioural (B) Source that references a specific net name.

@Tutorials: Whatever - just make the netname displayed on the schematic the same as whats currently displayed on the related PCB drawing. @Andy: Regarding simulations no doubt you are correct, my point is directed at making traceability and debugging between schematic and PCB drawings easier and less time consuming. Obviously there needs to be consistency with simulations as well. Somewhere a net has to have a "master" definition, I would have thought this happens in the schematic.

`Somewhere a net has to have a "master" definition, I would have thought this happens in the schematic.` That's correct. The schematic is effectively the master document. In effect the Schematic creates the PCB. The name assigned to a net in a schematic is passed through to the PCB. Similarly the PCB footprint assigned to each schematic symbol is what pulls in the footprints when the schematic is passed through to PCB. Changes to the footprints in the PCB are effected by changing the footprints assigned to the symbols and then using the Update PCB button in the schematic. The overwriting of net names by VolProbe names is a side effect of the way that the netlist is processed in the server.

+1 (for the original request to show netnames on wires in the schematic editor).

Thanks Andy.