If the simulated potentiometer is set to 0% or 100% an error message is generated because there is no protection against the one or the other of the two internal resistances dropping to zero. This problem was dealt with in EasyEDA before about V6 but the pot subckt has been rewritten and has missed this protection out. This is the subckt as it is now: ``` .SUBCKT Potentiometer_%s 1 2 3 val=%s k=%s R1 3 2  {val-(val*k)} R2 2 1  {val*k} .ENDS ``` Please replace it with this subckt which will protect again these zero resistance errors: ``` .SUBCKT Potentiometer_%s 1 2 3 val=%s k=%s ** * 1 = top end: slider fully clockwise * 2 = bottom end: slider fully anti-clockwise * 3 = slider * Limit function to prevent K1 and * Includes 1m resistors to stop zero resistance error at K=0 and K=1 * pin descriptions added and resistor names changed for clarity * signality.co.uk ** .param klim=LIMIT(0, k, 1) Rtop 1 3  {val-(val*klim)+1m} Rbot 3 2  {val*klim+1m} .ENDS ```