@BN, Welcome to EasyEDA. "It is stated in the simulation intro that it is not possible to simulate digital circuits in EasyEDA." I think you misread the Preliminary Remarks in the Simulation Tutorial. Simulation of digital circuits is very much possible using EasyEDA but it is not the best tool for trying to model clocked devices with complex internal states programmable devices such as microcontroller. Such devices require far too much processor time to simulate using spice simulation tools even when using the built-in digital modelling features of simulators like LTspice or Ngspice. That said there are spice symbol  libraries in EasyEDA with detailed behavioural models of 74HC and 4000 series devices many of which are in fact modelled as state machines. There are also a couple of ADC and DAC device models. Coming back to your question however, simulations of PCBs traces and device interfaces can be done in EasyEDA but you have to appreciate that it is a labour intensive task because you have to find the PCB dielectric and copper parameters to calculate the trace impedance and lengths and then manually implement those parameters in individual transmission line segments to map the PCB back into a representative schematic. Running the simulation from there is easy. There may be better tools for this such as the high end tools from Keysight, Mentor and Cadence but of course they are expensive. QUCS may be a more suitable tool because it has some dedicated substrate and physical transmission line modelling features but it has no interfaces to create properly documented schematics including BoM and PCB Footprint information nor any way to interface to a PCB layout tool.

If you think of what you are interested in simulating then you'll realise that this is in fact an analogue simulation  task anyway because any "digital " circuit when you look at it at a small enough timescale or run it fast enough must be seen as an analogue system.

@andyfierman Correct, I expressed myself badly. I was referring to the comment about DSP and uProcessors. Good that it is possible to simulate the PCB. I have been using qucs-s before to simulate schematics with lumped components, so I am familiar with how this is done. Could you direct me to a document (if it exists) that describes the modelling of PCB segments into an equivalent schematic? I need to simulate a straight 0.25mm wide line 50mm long with ground planes on each side,  single layer 2mm thick epoxy 35um Cu. This line will be driven by a SN74ALS541 bus buffer. This line will be connected via a header pin to a PaspberryPI hat, currently no RPI involved, only the hat. I need to see how the line should be terminated. I understand that reality will be much more complicated than this, since the pin going up to the hat is a significant transition in impedance. But I have to start somewhere. BN

@bnilsson11, There's no specific document in EasyEDA describing how to model PCB tracks. So I guess this is it... :) Please note that in the course of writing the notes below, I have discovered that the Tline model in EasyEDA is broken. I have posted a Bug Report about his here: [https://easyeda.com/forum/topic/Please-fix-the-Lossless-Transmission-Line-Tline-symbol-and-parameter-passing-to-the-model-221282cb41894fdf8e4fd2ea5868b106](https://easyeda.com/forum/topic/Please-fix-the-Lossless-Transmission-Line-Tline-symbol-and-parameter-passing-to-the-model-221282cb41894fdf8e4fd2ea5868b106) However, since this type of modelling tends to piecemeal in that it is not usually carried out on the whole of a schematic that is to be converted into a PCB there is actually no reason why this simulation work could not be better carried out on a local installation of LTspiceXVII or Qucs-S following the same procedure as outlined below. **How to model controlled impedance tracks** For most simulations of controlled impedance tracks a lossless transmission line model is all that is required to simulate the trace. A lossy, RLGC model can be used if the characteritics of the line can be calculated or measured in more detail but this is usually only required in special circumstances such as very long lines or operation at the upper end of a material's frequency range. In fact the G component is often not implemented in the spice RLGC models as it can usually be ignored. In most simulations it is the detailed characteristics of the signal source and the line termination that will have the greatest effect on the signal integrity. Any discontinuities caused by varations in trace width and transitions through vias and connectors can often be modelled simply by inserting short propagation delay lengths of different impednces or by breaking the line up into shorter delay time segments and connecting small capacitances to ground and small inductances in series to simulate the discontinuities. Thee is a very simple example of a transmission line with discontinuities here: [https://easyeda.com/editor#mode=sim,id=5ba8dcb605a34936983729f2f3e3776a](https://easyeda.com/editor#mode=sim,id=5ba8dcb605a34936983729f2f3e3776a) **How to design controlled impedance tracks** The basic physical parameters required to design controlled impedance PCB tracks are: Transmission line structure (surface/covered/buried/differential/coplanar microstrip, simple/offset/edge-coupled/broadside-coupled stripline); Copper thickness (on each layer); Spacings between the relevant copper layers; Dielectric constant(s) of the substrate layer(s) between the relevant copper layers; Trace spacings to ground planes and other transmission line elements; Trace width; Trace length; Once the transmission line structure has been chosen, the spacings between the relevant copper layers and the dielectric constant(s) of the substrate layer(s) between them can be found by querying the PCB manufacturer's information about board stackups and materials. Note: if a PCB manufacturer does not publish information about their board stackups and materials then it is very unlikely that they are going to be a suitable supplier of controlled impedance boards. Trace spacings and width can then be calculated pretty accurately using free tools like MWI2020 ([https://rogerscorp.com/Tools](https://rogerscorp.com/Tools)) and MLDTLC (Multi-Layer Dielectric Transmission Line Calculator field solver tool: [http://mdtlc.sourceforge.net/](http://mdtlc.sourceforge.net/)). There are many other free calculators but be careful to check the validity of their underlying calculations as the formulas used by some are only applicable for certain trace width to separation ratios). Once those calculations have been done, the trace width is known for a controlled impedance track on a given PCB substrate and stackup so the board can then be laid out and routed. From the layer dielectric properties, it is a simple matter to calculate the propagagtion delay in terms of s/m from: tpd = sqrt(Dk)/c Where: Dk is the dielectric constant of the material; c is the speed of light in free space = 2.998E8 m/s. Once routing has been completed, the trace lengths can be measured using the tools available. The measured trace lengths can then be used to calculate the propagation delays along the trace from: tpd = sqrt(Dk)/c Where: Dk is the dielectric constant of the material; c is the speed of light in free space = 2.998e8 m/s ( or 1.180e10 in/s). The calculated propagation delays can then be entered direcctly into the transmission line models in the simulation.

Thanks a lot, your answer seems to cover it all. Lots of studying to do, I will have fun trying it out.:) BN

I did an exercise in post-PCB-layout simulation some years ago and I found it helpful to put all the information about the PCB, stackup, track widths and lengths into a spreadsheet just to keep it clear. I added some sanity checking calculations about layer dimensions and cross checks with some advanced impedance calculations from Howard Johnson's High Speed Digital Design book.