Using v6.4.25
I am trying to lay out a 4-layer board with inner layers named 'GND' and 'VCC'.
It appears to me that vias with net named 'GND' connect to both inner planes and vias with net named 'VCC' connect to neither inner plane.
I'm assuming that I am missing something simple and fundamental.
Here's a minimalist example:
[https://oshwlab.com/conormcquaid/vcc-plane-test](https://oshwlab.com/conormcquaid/vcc-plane-test)
Chrome
93.0.4577.82
Linux
EasyEDA
6.4.25