The errors are telling you that there are incorrect time values in you PWL sources. Please check your PWL source values. The time values must increase monotonically; each value must be greater than the previous one. Are you sure that you have not made a mistake in editing the time values when you changed the V1 and V2 source voltage values?

The messages are telling you that your V1 and V2 PWL sources contain time values that are non-monotonic. In the PWL source any time value must be greater than the previous one. Please check your time points. Hint: try using a simpler pair of input signals such a pair of simple PULSE sources generating a square wave with one a quarter cycle delayed.

Please also see: https://easyeda.com/Doc/Simulation-eBook/Configuring-Voltage-and-Current-Sources.htm#Configuring-the-PWL-option

Sorry about the double reply about the time points: my first post took a while to appear and I thought I had messed up posting it. Here is a thought. What happens is if you build your flip-flop using the SCHMITTNAND2EE_mod02 gates? Leave the PWLs the same, just change the gates. Do you get the same error messages?

Ok, first I ckeck my PWL alone : all is ok, waveforms are correct. **With SCHMITTNAND2EE_mod02** simulation : tran 0.1 30 at 5 and 6V suply : simulation shows only waveforms for 2s at 7V suply : simulation shows only waveforms for 6s over 8V supply : same errors "*Warning : voltage source v2 has non-increasing PWL time points.*" Then I tried to change to tran 0.01 30 (just for fun ??) below 11V : simulation is now ok at 12V : same errors. With NOR2EE : changing tran 0.1 30 to 0.01 30 gives no changes (ok below 8V) Nothing more at the moment....

Hi, I just made some other tests (with NOR2EE) below 8V supply, simulation gices good waveforms BUT in the simulation result file, there are still errors : "Warning : voltage source v2 has non-increasing PWL time points." idem for V1 So I tried to create trise and tfall times in the PWL sources : V1 : PWL(0 0 2 0 2.01 12 3 12 3.01 0 5 0 5.01 12 7 12 7.01 0 8 0 8.01 12 10 12 10.01 0) V2 : PWL(0 12 1 12 1.01 0 4 0 4.01 12 6 12 6.01 0 9 0 9.01 12 11 12 11.01 0) And this time, no more "non-increasing PWL time points" error in the result file. But even with "now good" PWL, simulation fails to create waveforms over 9V supply. And creates a error listing..... I join the file in the project : "Error File 2.txt" (*"Simulation is too large...."*) Thank you for your help.

for easier tests I create 2 schematics : NOR flipflop - pow 9V + trise/fall and NOR flipflop - pow 8V + trise/fall files from simulation are : Simul File Error.txt and Simul File OK.txt The public project is https://easyeda.com/my-projects/ma4YgasJ1 JM

Yes, your original PWL sources had voltages that required instantaneous rise and fall transitions. In other words the first point of the transition occurred at the same time as the last point. This meant that you you had duplicate or non-increasing time points. Hence the error. I am looking into the other sources of error.

With 9V power : I add "uic" to sim conditions (tran 0.01 15 uic) then simulation works and plots are ok (!!) Sim file shows juste this "Warning: v1: no DC value, transient time 0 value used" but no errors. But still errors with 10V and more....

Instead of the UIC statement, try making the VDD voltage source like this: PULSE(0 12) This starts up the VDD rail from 0V.

Same error with Pulse, even with delay..... and rise time...

Hi Andy, I tested with 2 pulse sources delayed a quarter period. The result is the same : error when supply voltage is over 9V. And I tried analysis for DC operation point : There is a convergence problem ! 2 Pulse sources alone works well. With ONE NOR2EE gate, all is correct. The problem occurs when connecting 2 gates for a flip flop.... ! And with DC error.... no mre simulation for transient ! JM

Last tests : the project is here : [Supply_value_creates_simulation_errors_for_a_NOR_flipFlop][2] "2 square delayed with uic" : works below 10V. (see result waves below) "2 square delayed without uic" : see error file : "2 square delayed error file.txt" (convergence problems) I don't see what I can do now.... Thank you for help.... JM ![enter image description here][1] [1]: /editor/20160413/570d2ea98bb3f.png [2]: https://easyeda.com/jmter/Supply_value_creates_simulation_errors_for_a_NOR_flipFlop-ma4YgasJ1

Please try those same two sims again now. I have adjusted the NOR2EE model in the library and will do some more edits tomorrow. Let me know how it goes?

The modified model will still fail in a flip flop if both S and R rising edges are exactly coincident, i.e. they both rise together with the same rise times. This may be why some of your sims fail to converge: do you have any such cases in your PWL sources? I think suspect that this *may* reflect real device behaviour due to metastability in the flip flop configuration where if both gates are enabled at exactly the same time they may oscillate with a period of twice the propagation delay but I need to investigate more.

With the new NOR2EE it is now ok in regards to supply voltage (12V and more) With the followings sources for R and S : 1-PWL (as my needs) **without** rise and fall times (non-increasing PWL time points) but waveforms are ok ;-) ! PWL(0 0 2 0 2.01 12 3 12 3.01 0 5 0 5.01 12 7 12 7.01 0 8 0 8.01 12 10 12 10.01 0) PWL(0 12 1 12 1.01 0 4 0 4.01 12 6 12 6.01 0 9 0 9.01 12 11 12 11.01 0) ==> OK with or without UIC statement 2-PWL (as my needs) **with** rise and fall times : PWL(0 0 2 0 2.01 12 3 12 3.01 0 5 0 5.01 12 7 12 7.01 0 8 0 8.01 12 10 12 10.01 0) PWL(0 12 1 12 1.01 0 4 0 4.01 12 6 12 6.01 0 9 0 9.01 12 11 12 11.01 0) ==> OK with or without UIC statement 3-PWL configured as **square and delayed** PULSE(0 12 0 100n 100n {1s-100n} 2s) PULSE(0 12 0.5s 100n 100n {1s-100n} 2s) ==> OK with UIC statement **==> ERROR without UIC statement** : convergence problems.... (see txt file in the project or SIM result below) But no simultaneous edges for R and S... ![enter image description here][1] the project is here : https://easyeda.com/jmter/NOR_flipFlop_with_different_PWL_sources-a2eOMlVTt **SIM Result :** ---------- Circuit: untitled Reducing trtol to 1 for xspice 'A' devices Doing analysis at TEMP = 27.000000 and TNOM = 27.000000 Warning: v1: no DC value, transient time 0 value used Warning: v2: no DC value, transient time 0 value used Warning: Too many analog/event-driven solution alternations WARNING: Convergence problems at node (xu2.in1d). Instance: a.xu2.a.xin1.aadc1 Connection: out Port: 0 WARNING: Convergence problems at node (xu1.in2d). Instance: a.xu1.a.xin2.aadc1 Connection: out Port: 0 Transient solution failed - Last Node Voltages ------------------ Node Last Voltage Previous Iter ---- ------------ ------------- vdd 12 12 xu1_5 12 12 xu2.xin1.inunity1 1 1 r 0 0 xu2.xin2.inunity1 0 0 xu2.vddok 1 1 xu2.xout1.pullupswa1 1 1 xu2.xout1.pulldownswa1 0 0 xu2.xout1.multswhi1 4.605 4.605 xu2.xout1.multswlo1 0 0 q 12 12 s 0 0 xu1.xin1.inunity1 0 0 xu1.xin2.inunity1 1 1 xu1.vddok 1 1 xu1.xout1.pullupswa1 1 1 xu1.xout1.pulldownswa1 0 0 xu1.xout1.multswhi1 4.605 4.605 xu1.xout1.multswlo1 0 0 v1#branch 1.9e-11 1.9e-11 v2#branch 1.9e-11 1.9e-11 v3#branch -4.41265e-08 -4.41265e-08 a.xu1.a.xin2.ainunityscale1#branch_2_0 0 0 a.xu1.a.xin1.ainunityscale1#branch_2_0 0 0 a.xu2.a.xin2.ainunityscale1#branch_2_0 0 0 a.xu2.a.xin1.ainunityscale1#branch_2_0 0 0 a.xu1.ahyst1#branch_1_0 0 0 a.xu2.ahyst1#branch_1_0 0 0 a.xu1.a.xout1.amultlo1#branch_1_0 0 0 a.xu1.a.xout1.amulthi1#branch_1_0 0 0 a.xu2.a.xout1.amultlo1#branch_1_0 0 0 a.xu2.a.xout1.amulthi1#branch_1_0 0 0 a.xu1.a.xout1.adac2#branch_1_0 0 0 a.xu1.a.xout1.adac1#branch_1_0 0 0 a.xu2.a.xout1.adac2#branch_1_0 0 0 a.xu2.a.xout1.adac1#branch_1_0 0 0 doAnalyses: iteration limit reached tran simulation(s) aborted Error(parse.c--checkvalid): q: no such vector. ngspice-26 done ---------- [1]: /editor/20160413/570de9220f492.png

Yes, that's what I found. If you make the supply ramp up using: `PULSE(0 {vdd})` then your 3-PWL configured as square and delayed PULSE(0 12 0 100n 100n {1s-100n} 2s) PULSE(0 12 0.5s 100n 100n {1s-100n} 2s) runs OK too. You can play with these cases here: https://easyeda.com/andyfierman/Jmter_NOR_flip_flop_problem-eqICqeK1j I have also updated the NOR2EE model to remove the `~` form of the inverter stage so that you can now copy and paste it into your schematic should you wish to tinker with it further.

Thank you again for the job. All is working now. I have just to write down some solutions... witch can solve some problems.... : - be carefull with rise and fall times for PWL & pulse sources - use pulse(0 vdd) instead of DC power sources - sometimes using uic will be usefull - capacitors (and inducotors) need to have ic - ... **My next concern is about translation.** Long time ago, I made the french translation (for my young students). But a lot af new features have been added. The french version is a mix with english ! I hope you will propose a way to translate EasyEDA soon !

A couple of comments: - be carefull with rise and fall times for PWL & pulse sources For more, please have a look at: https://easyeda.com/Doc/Simulation-eBook/Configuring-Voltage-and-Current-Sources.htm#Configuring-Voltage-and-Current-Sources - use pulse(0 vdd) instead of DC power sources Use only for transient simulations. In AC simulations the circuit will have no power as you run the analysis and so will give misleading results! In transient simulations this is not always necessary. Many simulations will run with a simple DC source but it can be invaluable for getting difficult sims to start! (This is what the `Startup` option in LTspice does.) If it *is* needed then sometimes you may also need to add a risetime: `pulse(0 vdd 0 tr)` Sometimes you may only need to generate a short pulse like this: `pulse(vdd {vdd+0.1V} 0 tr tf ton)` (Have a look at the `Xtalfast` subckt used for the crystal component in EasyEDA Libs for an extreme example of this technique.) - sometimes using uic will be usefull For more, please have a look at: https://easyeda.com/Doc/Simulation-eBook/Setting-up-Analyses.htm#5-TRAN-Perform-a-Transient-time-domain-Analysis and: https://easyeda.com/Doc/Simulation-eBook/Setting-up-Analyses.htm#IC-Set-Initial-Conditions - capacitors (and inducotors) need to have ic https://easyeda.com/Doc/Simulation-eBook/Initial-conditions-and-starting-up-circuits.htm#Initial-conditions-and-starting-up-circuits As for translations: we have to rely quite heavily on user contributions... ...but you (or your students) can earn lots of private projects! :)

At the moment, I can not make the project as public ! I don't want they find the final solution. At the moment, I prepare a "not finish" project I will give them as public. And they will have to complete and simulate. I'm not sure to understand the meaning of your last sentence ? (my english level is maybe not so good to understand refinements)

`At the moment, I can not make the project as public!` `I don't want they find the final solution.` Exactly! In EasyEDA you are allowed only a small number of private projects*. But right now, all EasyEDA users can earn more private projects by doing things like: - contributing high quality, well documented, projects, schematic symbols or modules, PCB footprints or modules; - helping to write documentation; - contributing to translations (as you have already). :) * Soon you will be able to get more private projects by paying a small subscription (the amount/month is still being discussed).

Ok that's fine. Concerning the subscription, I hope it will not be too expensive :)) I tested some ways to share files : First I export my design as EasyEDA source file (.json) Then I send it to another user. He has just to "Open EasyEDA file..." from design menu ! Another way for the other user is to open a "New Shematic", clic "Open EasyEDA file..." in design menu... Then paste and Apply.... That's it ! So there are many ways to share designs and files... EasyEDA is a great solution. A few precision : In my HighScool most of my colleagues works Orcad. My favortie is Eagle (but without simulation) And since I know EasyEDA, I try to use it... I hope it will be THE unique tool !