Hi,
I would like to use a TSV621 op-amp in my simulation.
I watched: [010 Simulation Library - YouTube](https://www.youtube.com/watch?v=TYhSQhkVWUE) and I understand that I have to copy the SPice simulation file under "Edit -> Spice model".
The SPice macromodel is available here: [TSV621 - Rail-to-rail input/output 5V CMOS Op-Amp, micro-power (29uA), GBP=420kHz, single - STMicroelectronics](https://www.st.com/content/st_com/en/products/amplifiers-and-comparators/operational-amplifiers-op-amps/precision-op-amps-lt50-mhz/low-power-op-amps-lt1-ma/tsv621.html#cad-resources).
UM0065 states this macromodel is compatible with Pspice and SPice simulators.
Upon simulation of my circuit, the following pop-up appears:
![image.png](//image.easyeda.com/pullimage/Yvn58rJZP7ryvVG56wHAJiYE2h3hHNTpQLTGeGU8.png)
If I go back into the model of my TSV621 and open up "Edit -> Spice model" I notice the model has been truncated (the end has been removed)!
Maybe there is a length limit to the SPice model?
I would greatly appreciate any help in resolving this issue and having a functional TSV621 model.
Thank you,
Hugues
Edge Chromium
91.0.864.54
Windows
10
EasyEDA
6.4.19.4