Hello, I am very new to this program, when verifying I get the following problems:
"The free space between two objects is less than the verification free space of the DRC design rule that has different rules"
Could you tell me how to fix it?
it is about vias that connect a lower track with another upper
Thank you.
Hello Andy, thank you very much for responding so quickly, the attached menu I have configured the same way but the errors persist. What can I do?
I have the finished pcb ready for printing but I don't know if these errors will get it working.
thank you very much again
@juanaca,
Your screenshot does not shown enough detail and your project is private so only you can see it.
Can you make a public copy to demonstrate the problem and post the url to that project here?
Brand new interactions and interfaces. 
Easy to use and quick to get started. 
Please check how the Design Rules are set up for your PCB:
Try switching PCB Canvas units to "mil" then re-run the DRC: for small clearances you may see rounding errors.