Hello, I am very new to this program, when verifying I get the following problems:
"The free space between two objects is less than the verification free space of the DRC design rule that has different rules"
Could you tell me how to fix it?
it is about vias that connect a lower track with another upper
Thank you.![Captura de pantalla 2020-06-12 a las 12.49.04.png](//image.easyeda.com/pullimage/v5lafRrHgTdfrPeJbAPKbQzDCLVhi4KMuN2XU6JZ.png)![Captura de pantalla 2020-06-12 a las 12.48.59.png](//image.easyeda.com/pullimage/l1zXJQFmgwipSB9W4oz1I2AK8wRtNOAQKETS1yx1.png)
Chrome
83.0.4103.97
OS X
10_14_6
EasyEDA
6.3.53